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PCI Bus – supports Rev 2.2 spec and 4/ 6 (optional) master devices
Dual UltraDMA33/ 66 (optional) IDE controller
Dual USB controller (12Mbps or 1.5Mbps)
AC’97 link for audio/ telephony CODEC’s
SMbus controller (motherboard management)
Interrupt Controller – integrated I/O APIC capability
GPIO functions – TTL,
Enhanced DMA controller
ACPI power management logic
Low Pin Count (LPC) interface (Super I/O connection)
The second level cache is contained within the processor module. There is no provision for a third level cache. Cache size is determined by the type of CPU fitted, refer to your CPU manufacturer for this information.
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There are two DIMM sockets on the motherboards that accept
2 or 4 bank organisation
Asymmetric or symmetric memory addressing. Single or
MITSUBISHI ELECTRIC MOTHERBOARD DIVISION | PAGE 18 OF 45 |