Specifications |
Analog input/output calibration
| Table 24. Analog input/output calibration specifications | |
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Parameter |
| Specifications |
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Recommended |
| 45 minutes minimum |
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Calibration |
| Firmware calibration |
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Calibration interval |
| 1 year |
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Calibration reference |
| +10.000 V, ±5 mV maximum. Actual measured values stored in EEPROM |
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| Tempco: 5 ppm/°C maximum |
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| Long term stability: 30 ppm/1000 hours |
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Digital input/output
| Table 25. Digital input specifications |
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Number of I/O | 8 channels |
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Configuration | Each DIO bit can be independently read from (DIN) or written to (DOUT). |
| The DIN bits can be read at any time whether the DOUT is active or |
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Input voltage range | 0 to +15 V |
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Input type | CMOS (Schmitt trigger) |
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Input characteristics | 47 kΩ |
Maximum input voltage range | 0 to +20 V maximum (power on/off, relative to DGND pins 93 and 94) |
All pins pulled up to +5 V via individual 47 kΩ resistors (the JP1 shorting block | |
configuration | default position is pins 1 and 2). |
| Pull down capability is available by placing the JP1 shorting block across pins 2 and 3. |
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Transfer rate (software paced) | 500 port reads or single bit reads per second typical. |
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Input high voltage | 1.3 V minimum, 2.2 V maximum |
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Input low voltage | 1.5 V maximum, 0.6 V minimum |
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Schmitt trigger hysteresis | 0.4 V minimum, 1.2 V maximum |
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Note 2: DGND pins (pins 93, 94) are recommended for use with digital input and digital output pins. The DGND and GND pins are common and are isolated from earth ground.
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| Table 26. Digital output specifications |
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Number of I/O | 8 channels | |
Configuration | Each DIO bit can be independently read from (DIN) or written to (DOUT). | |
| The DIN bits may be read at any time whether the DOUT is active or | |
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Output characteristics | 47 kΩ | |
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All pins pulled up to +5 V via individual 47 kΩ resistors (the JP1 shorting block | ||
| default position is pins 1 and 2). | |
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Transfer rate (software paced) | Digital output – 500 port writes or | |
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Output voltage range | 0 to +5 V (no external pull up resistor, internal 47 kΩ | |
| +5 V by default) | |
| 0 to +15 V maximum (Note 5) | |
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Drain to source breakdown | +50 V minimum | |
voltage |
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Off state leakage current | 0.1 µA | |
(Note 6) |
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Sink current capability | | 150 mA maximum (continuous) per output pin |
| | 150 mA maximum (continuous) for all eight channels |
DMOS transistor | 4 Ω | |
(drain to source) |
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Note 3: Each DMOS transistor’s source pin is internally connected to GND. |
Note 4: DGND pins (pins 93, 94) are recommended for use with digital input and digital output pins. The DGND and GND pins are common and are isolated from earth ground.
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