1998 July 30
Philips Semiconductors Objective Specification, Revision 2.2
Pre-Amplifier for Hard Disk Drive with
MR-Read / Inductive Write Heads TDA5360
24
11 SERIAL INTERFACE TIMING
0...Reg.00H
SEN
SCLK
SDATA
a0=0 a2a1 a3 a4 a5 a6 a7
Address Data
1 Tclk 0.5 Tclk
d0 d1 d2 d3 d4 d5 d5 d7
SEN
SCLK
SDATA
a0=1 a2a1 a3 a4 a5 a6 a7
Address Data
2 Tclk
1.5 Tclk
d0 d1 d2 d3 d4 d5 d6 d7
READ
WRITE
t > 5ns t > 5ns
When Fclk > 20 MHz and a register reading is performed, it is necessary to extend the clock period as above
When Fclk < 20 MHz, this is not necessary
1 Tclk