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Pico Communications E-14 manual E‐14 Hardware Reference Manual, Pico Computing, Inc

Models: E-14

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E‐14 Hardware Reference Manual

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Pico Computing, Inc.

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Pico Communications E-14 manual E‐14 Hardware Reference Manual, Pico Computing, Inc

Contents

Release Hardware Version F E‐14Hardware Technical Reference Pico E14 Hardware ReferenceI/O Interfaces ContentsFeatures AppendicesProduct Overview Features Pico E-14 EP Quick Reference DatasheetMechanical Specification Core TechnologiesPower W Pico E‐14 Electrical SpecificationsPower Consumption Power WDSP Slices System ArchitectureDDR2 RAM Flash ROM FPGA Fabric Field Programmable Gate ArrayFPGA Resources DSP SlicePowerPC Processor PPC405x3 Processor IntroductionE‐14 Hardware Reference Manual CPLD TurboLoaderCPLD Resources Pico Computing, IncTri‐Mode Ethernet Interface Ethernet ResourcesByte addresses Flash MemoryTypical Flash ROM Allocation Table DescriptionFPGA DDR2 MemoryBank Bank8‐Bit, 80 MSPS Analog‐to‐Digital Converter ADC Analog Interface Optional8‐Bit, 165 MSPS Digital‐to‐Analog Converter DAC RS‐232 Serial Transceiver 1 Tx / 1 RxDIAGEN State Digital Peripheral InterfaceElectrical Specifications JTAGCardBus Interface PCMCIA Interface ResourcesMinimum Digital Bus InterfaceElectrical Specifications DC NominalTurbo Loader IR= JTAG Debug InterfaceFPGA PowerPC Ethernet IR=Description Appendix A - Peripheral I/O Connector InformationNOTE Pin 1 indicator on the board is actually Pin 32 indicator BrandBrand Appendix B - CardBus Connector InformationDescription Part NumberDescription CardBus Connector Pull Up and Pull Down InformationName ValueE‐14 Hardware Reference Manual Pico Computing, IncAppendix C - FPGA Pinout FPGA PinoutPage Page Page Page Page Page Description Appendix D - CPLD PinoutCPLD Pinout DirectionSLEEP Sleep Mode RequestPin D15 turns into Address ‐1 when the Flash ROM is in 8 bit mode E‐14 Hardware Reference ManualStandard Part Number Listing Appendix E - Standard Part Number ListingPico E‐14 EP E‐14 Hardware Reference Manual Appendix F - ErrataAll versions Pico Computing, IncPower Requirements Appendix G - FPGA Performance EnhancementsHeat Sink Placement OverviewLow Power Appendix E - Analog Interface Selection GuideResolution bits Part14.1.8.12 Revision History14.1.8.11 E‐14 Hardware Reference ManualLegal Notices This manual is 2005 Pico Computing, Inc