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Pico Communications E-14 manual Appendix F - Errata, All versions, E‐14 Hardware Reference Manual

Models: E-14

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Appendix F – Errata

The following section lists all known errata:

All versions:

Permanent damage will result if the Pico E‐14 is left un‐configured and powered on for more than 10 minutes. This should not be a problem since the Pico E‐14 automatically loads an FPGA image upon power‐on.

E‐14 Hardware Reference Manual

www.picocomputing.com

Pico Computing, Inc.

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Pico Communications E-14 manual Appendix F - Errata, All versions, E‐14 Hardware Reference Manual, Pico Computing, Inc

Contents

Hardware Technical Reference E‐14Release Hardware Version F Pico E14 Hardware ReferenceFeatures ContentsI/O Interfaces AppendicesProduct Overview Mechanical Specification Pico E-14 EP Quick Reference DatasheetFeatures Core TechnologiesPower Consumption Pico E‐14 Electrical SpecificationsPower W Power WSystem Architecture DSP SlicesDDR2 RAM Flash ROM FPGA Resources Field Programmable Gate ArrayFPGA Fabric DSP SlicePPC405x3 Processor Introduction PowerPC ProcessorCPLD Resources CPLD TurboLoaderE‐14 Hardware Reference Manual Pico Computing, IncEthernet Resources Tri‐Mode Ethernet InterfaceTypical Flash ROM Allocation Table Flash MemoryByte addresses DescriptionBank DDR2 MemoryFPGA BankAnalog Interface Optional 8‐Bit, 80 MSPS Analog‐to‐Digital Converter ADC8‐Bit, 165 MSPS Digital‐to‐Analog Converter DAC 1 Tx / 1 Rx RS‐232 Serial TransceiverElectrical Specifications Digital Peripheral InterfaceDIAGEN State JTAGPCMCIA Interface Resources CardBus InterfaceElectrical Specifications DC Digital Bus InterfaceMinimum NominalFPGA PowerPC JTAG Debug InterfaceTurbo Loader IR= Ethernet IR=NOTE Pin 1 indicator on the board is actually Pin 32 indicator Appendix A - Peripheral I/O Connector InformationDescription BrandDescription Appendix B - CardBus Connector InformationBrand Part NumberName CardBus Connector Pull Up and Pull Down InformationDescription ValuePico Computing, Inc E‐14 Hardware Reference ManualFPGA Pinout Appendix C - FPGA PinoutPage Page Page Page Page Page CPLD Pinout Appendix D - CPLD PinoutDescription DirectionPin D15 turns into Address ‐1 when the Flash ROM is in 8 bit mode Sleep Mode RequestSLEEP E‐14 Hardware Reference ManualAppendix E - Standard Part Number Listing Standard Part Number ListingPico E‐14 EP All versions Appendix F - ErrataE‐14 Hardware Reference Manual Pico Computing, IncHeat Sink Placement Appendix G - FPGA Performance EnhancementsPower Requirements OverviewResolution bits Appendix E - Analog Interface Selection GuideLow Power Part14.1.8.11 Revision History14.1.8.12 E‐14 Hardware Reference ManualThis manual is 2005 Pico Computing, Inc Legal Notices