Quatech DS-102 Accessing the Serial Port registers

Accessing the Serial Port registers

Figure 15 lists the address map for the 16450 and 16550 UARTs.

Each register can be accessed by reading from or writing to the proper

I/O address. This I/O address is determined by adding an offset to the

base address set for the particular serial port. The base address is set

using DIP switches on the DS-102 (see section III).

Notice that two locations access different registers depending on

whether an I/O read or I/O write is attempted. Address [base+0]

accesses the receive buffer on an I/O read, or the transmit buffer on an

I/O write. Address [base+2] accesses the Interrupt Identification register

on an I/O read or the FIFO control register (16550 only) on an I/O write.

Also, notice that if address [base+0] or [base+1] is used with the DLAB bit

from the Line Control Register set to '1', the baud rate divisor latches are

accessed.

NOTE: All figures displaying bitmapped registers are

formatted such that bit 7 is the high-order bit.

DLAB

in Line Control Register must be set to access baud rate divisor latch.

(X = don't care)

Baud rate divisor latch (MSB) *Base + 11

Baud rate divisor latch (LSB) *Base + 01

ScratchpadBase + 7X

MODEM statusBase + 6X

Line statusBase + 5X

MODEM controlBase + 4X

Line control

Base + 3

Interrupt identification (read) (16450 and 16550)

FIFO control (write) (16550 only)

Base + 2

Interrupt enable

Base + 1

Receive buffer (read)

Transmit holding register (write)

Base + 0

I/O Address

DLAB

UART

Addressing

Figure 15 --- Serial port register address map for 16450/16550 UART

Quatech

DS-102 User's Manual