Quatech DS-102

WARRANTY INFORMATION

Quatech, Inc. warrants the DS-102 to be free of defects for

one (1) year from the date of purchase. Quatech, Inc. will repair or

replace any board that fails to perform under normal operating conditions

and in accordance with the procedures outlined in this document during

the warranty period. Any damage that results from improper installation,

operation, or general misuse voids all warranty rights.

Please complete the following information and retain for your

records. Have this information available when requesting warranty

service.

DATE OF PURCHASE:

MODEL NUMBER: DS-102

PRODUCT DESCRIPTION: Dual Channel RS-232 Asynchronous

Communications Adapter

SERIAL NUMBER:

Quatech

DS-102 User's Manual

Contents

Main Page VIII. TROUBLESHOOTING V. EXTERNAL CONNECTIONS VII. SPECIFICATIONS VI. SERIAL PORT FUNCTIONAL DESCRIPTION IV. SETTING INTERRUPT LEVELS (IRQS) Page Page Page I.GENERAL INFORMATION II.INSTALLATION Figure 2 --- Diagram of DS-102 III.ENABLING AND ADDRESSING PORTS Setting the address Serial 2 uses SW2 SW1 5 SW2 Figure 4 --- Serial Port base I/O address selection switches J4 Page IV.SETTING INTERRUPT LEVELS (IRQS) J5 Serial 2 J6 Serial 1 Interrupt Sharing Serial 1 uses J2 Serial 2 uses J3 V.EXTERNAL CONNECTIONS DS-102 User's Manual Figure 11 --- Cabling requirements for RS-232-C devices (cables using 25-pin connectors shown) 10 Quatech J7 -- Serial 1 J8 -- Serial 2 Figure 13 --- DS-102 connector definitions for RS-232-C Figure 14 --- DS-102 Output connectors Page VI.SERIAL PORT FUNCTIONAL DESCRIPTION Accessing the Serial Port registers INTERRUPT ENABLE REGISTER INTERRUPT IDENTIFICATION REGISTER Figure 18 --- IIDx bit decoding FIFO CONTROL REGISTER (16550 only) Figure 19 --- 16550 FIFO Control Register bit definitions LINE CONTROL REGISTER Figure 20 --- Line Control Register bit definitions MODEM CONTROL REGISTER LINE STATUS REGISTER MODEM STATUS REGISTER SCRATCHPAD REGISTER FIFO INTERRUPT MODE OPERATION (16550 UART only) FIFO polled mode operation (16550 UART only) BAUD RATE SELECTION J1 Figure 25 --- Divisor Latch settings for common baud rates using 1.8432 MHz input clock VII.SPECIFICATIONS VIII. TROUBLESHOOTING