Quatech DS-102 J1

The 16450 or 16550 UART determines the baud rate of the serial

output using a combination of the clock input frequency and the value

written to the divisor latches. Standard personal computer serial

interfaces use an input clock of 1.8432 MHz. To increase versatility, the

DS-102 uses an 18.432 MHz crystal and a frequency divider circuit to

produce the standard clock frequency.

Jumper block J1 is used to set the frequency input to the UART. It

may be connected to divide the clock input by 1, 2, 5, or 10. A table of

baud rates available using the 1.8432 MHz input is given in Figure 25.

For compatibility with standard serial ports, J1 should be

configured to divide by 10 as shown in Figure 24 (d).

Divide-by-1 input clock Divide-by-2 input clock

(A) (B)

465

(C)

(D)

Divide-by-5 input clock Divide-by-10 input clock

Factory default

12 3

456

465

Figure 24 --- Input clock frequency options

Quatech

DS-102 User's Manual

Contents

Main Page VIII. TROUBLESHOOTING V. EXTERNAL CONNECTIONS VII. SPECIFICATIONS VI. SERIAL PORT FUNCTIONAL DESCRIPTION IV. SETTING INTERRUPT LEVELS (IRQS) Page Page Page I.GENERAL INFORMATION II.INSTALLATION Figure 2 --- Diagram of DS-102 III.ENABLING AND ADDRESSING PORTS Setting the address Serial 2 uses SW2 SW1 5 SW2 Figure 4 --- Serial Port base I/O address selection switches J4 Page IV.SETTING INTERRUPT LEVELS (IRQS) J5 Serial 2 J6 Serial 1 Interrupt Sharing Serial 1 uses J2 Serial 2 uses J3 V.EXTERNAL CONNECTIONS DS-102 User's Manual Figure 11 --- Cabling requirements for RS-232-C devices (cables using 25-pin connectors shown) 10 Quatech J7 -- Serial 1 J8 -- Serial 2 Figure 13 --- DS-102 connector definitions for RS-232-C Figure 14 --- DS-102 Output connectors Page VI.SERIAL PORT FUNCTIONAL DESCRIPTION Accessing the Serial Port registers INTERRUPT ENABLE REGISTER INTERRUPT IDENTIFICATION REGISTER Figure 18 --- IIDx bit decoding FIFO CONTROL REGISTER (16550 only) Figure 19 --- 16550 FIFO Control Register bit definitions LINE CONTROL REGISTER Figure 20 --- Line Control Register bit definitions MODEM CONTROL REGISTER LINE STATUS REGISTER MODEM STATUS REGISTER SCRATCHPAD REGISTER FIFO INTERRUPT MODE OPERATION (16550 UART only) FIFO polled mode operation (16550 UART only) BAUD RATE SELECTION J1 Figure 25 --- Divisor Latch settings for common baud rates using 1.8432 MHz input clock VII.SPECIFICATIONS VIII. TROUBLESHOOTING