Quatech DS-102 I.GENERAL INFORMATION

I.GENERAL INFORMATION

The Quatech, Inc. DS-102 provides two RS-232 asynchronous serial

communication interfaces for IBM-compatible personal computer systems

using the ISA (Industry Standard Architecture) expansion bus.

The DS-102's two serial ports are implemented using 16450

Universal Asynchronous Receiver/Transmitters (UARTs). For higher

performance, 16550 UARTs can be installed in place of the 16450 UARTs.

The 16550 contains a hardware buffer that reduces processing overhead.

Software must be aware of the 16550 UART for the device's extra

capabilities to be used, otherwise it will act as a 16450 UART. The 16550

is suggested for multitasking environments and for applications involving

high data rates.

The DS-102 is highly flexible with respect to addressing and

interrupt level use. The base I/O address of each serial port can be

independently set anywhere within the range of 0000 hex to 07FF hex,

and available interrupt levels include IRQ2 through IRQ7.

Quatech

DS-102 User's Manual

1

Contents

Main Page VIII. TROUBLESHOOTING V. EXTERNAL CONNECTIONS VII. SPECIFICATIONS VI. SERIAL PORT FUNCTIONAL DESCRIPTION IV. SETTING INTERRUPT LEVELS (IRQS) Page Page Page I.GENERAL INFORMATION II.INSTALLATION Figure 2 --- Diagram of DS-102 III.ENABLING AND ADDRESSING PORTS Setting the address Serial 2 uses SW2 SW1 5 SW2 Figure 4 --- Serial Port base I/O address selection switches J4 Page IV.SETTING INTERRUPT LEVELS (IRQS) J5 Serial 2 J6 Serial 1 Interrupt Sharing Serial 1 uses J2 Serial 2 uses J3 V.EXTERNAL CONNECTIONS DS-102 User's Manual Figure 11 --- Cabling requirements for RS-232-C devices (cables using 25-pin connectors shown) 10 Quatech J7 -- Serial 1 J8 -- Serial 2 Figure 13 --- DS-102 connector definitions for RS-232-C Figure 14 --- DS-102 Output connectors Page VI.SERIAL PORT FUNCTIONAL DESCRIPTION Accessing the Serial Port registers INTERRUPT ENABLE REGISTER INTERRUPT IDENTIFICATION REGISTER Figure 18 --- IIDx bit decoding FIFO CONTROL REGISTER (16550 only) Figure 19 --- 16550 FIFO Control Register bit definitions LINE CONTROL REGISTER Figure 20 --- Line Control Register bit definitions MODEM CONTROL REGISTER LINE STATUS REGISTER MODEM STATUS REGISTER SCRATCHPAD REGISTER FIFO INTERRUPT MODE OPERATION (16550 UART only) FIFO polled mode operation (16550 UART only) BAUD RATE SELECTION J1 Figure 25 --- Divisor Latch settings for common baud rates using 1.8432 MHz input clock VII.SPECIFICATIONS VIII. TROUBLESHOOTING