INTERRUPT ENABLE REGISTER
This register is located at I/O address [base+1]. It enables the five
types of UART interrupts. Interrupts can be totally disabled by setting all
of the enable bits in this register to a logic 0. Setting any bit to a logic 1
enables that particular interrupt.
ETBEI --- Received Data Available Interrupt:
When set (logic 1), enables interrupt on received data available. For
16550 FIFO mode, interrupts are also enabled for receive FIFO trigger
level reached and for receive timeout.
0
ETBEI --- Transmitter Holding Register Empty Interrupt:
When set (logic 1), enables interrupt on transmitter holding register
empty.
1
ELSI --- Receiver Line Status Interrupt:
When set (logic 1), enables interrupt on overrun, parity, framing
errors, and break indication.
2
EDSSI --- MODEM Status Interrupt:
When set (logic 1), enables interrupt on clear to send, data set ready,
ring indicator, and data carrier detect.
3
0 --- reserved
4
0 --- reserved
5
0 --- reserved
6
0 --- reserved
7
DESCRIPTION
BIT
Figure 16 --- Interrupt Enable Register bit definitions
INTERRUPT IDENTIFICATION REGISTER
This read-only register is located at I/O address [base+2]. When
this register is read, the UART freezes all interrupts and indicates the
highest priority interrupt. During this time, new interrupts are detected
by the UART, but are not reported in this register until the access
completes.
For the 16550 only, this register can be used to indicate whether
the FIFO mode is engaged by examining bits 6 and 7.
16
Quatech
DS-102 User's Manual