IP --- Interrupt pending:
When logic 0, indicates that an interrupt is pending and the contents of the
interrupt identification register may be used to determine the interrupt
source. See Figure 18.
0
IID0 ---
1
IID1 ---
2
Interrupt Identification:
Indicates highest priority interrupt pending if any. See Figure 18 .
NOTE: IID2 is always a logic 0 on the 16450 or in non-FIFO mode
on the 16550.
IID2 ---
3
0 --- reserved
4
0 --- reserved
5
FFE --- FIFO enable: (16550 only)
When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450.
6
FFE --- FIFO enable: (16550 only)
When logic 1, indicates FIFO mode enabled. Always logic 0 for the 16450.
7
DESCRIPTION
BIT
MODEM Status: Indicates clear to send, data set ready, ring
indicator, or data carrier detect have changed state. The
interrupt is cleared by reading the MODEM status register.
4th
0
0
0
0
Transmitter Holding Register Empty: Indicates the transmitter
holding register is empty. The interrupt is cleared by reading
the interrupt identification register or writing to the transmitter
holding register. (Indicates transmit FIFO empty for 16550.)
3rd
0
1
0
0
Character Timeout (16550 FIFO mode only): Indicates no
characters have been removed from or input to the receiver
FIFO for the last four character times and there is data present
in the receiver FIFO. The interrupt is cleared by reading the
receiver FIFO.
2nd
0
0
1
1
Received Data Ready (16450 or 16550): Indicates receive data
available. The interrupt is cleared by reading the receive buffer.
In 16550 FIFO mode, indicates the receiver FIFO trigger level
has been reached. The interrupt is reset when the FIFO drops
below the trigger level.
2nd0010
Receiver Line Status: Indicates overrun, parity, framing errors
or break interrupts. The interrupt is cleared by reading the line
status register.
1st0110
None
N/A1don't
care
012
Interrupt TypePriorityIPIIDx bits
Figure 18 --- IIDx bit decodingQuatech
DS-102 User's Manual
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