7.3 Power ON/OFF Sequence
To prevent a
0<T1≤10msec 0<T2≤50msec 0<T3≤50msec 1000msec≤T4
1000msec≤T5
(Recommend Value)2.4 V 100msec≤T6
(Recommend Value)
T1 : VDD rising time from 10% to 90%
T2 : The time from VDD to valid data at power ON.
T3 : The time from valid data off to VDD off at power Off.
T4 : VDD off time for Windows restart
T5 : The time from valid data to B/L enable at power ON.
T6 : The time from valid data off to B/L disable at power Off.
The supply voltage of the external system for the Module input should be the same as the definition of VDD.
Apply the lamp voltage within the LCD operation range. When the back light turns on before the LCD operation or the LCD turns off before the back light turns off,
the display may momentarily show abnormal screen.
In case of VDD = off level,
please keep the level of input signals low or keep a high impedance.
T4 should be measured after the Module has been fully discharged between power off and on period.
Interface signal should not be kept at high impedance when the power is on.
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