Silicon Image SSD-D32G(I)-4300 manual Signal Descriptions Continued, Signal Name, Pins, Type

ELECTRICAL SPECIFICATION				SSD-DXXX(I)-4300 DATA SHEET
		Table 8:	Signal Descriptions (Continued)
	Signal Name	Pin(s)	Type	Description
	DMARQ#			This signal is a DMA request that is used
	(UDMA			for DMA data transfers between the host
	protocol			and device. This signal is asserted by the
	active)			device when it is ready to transfer data to or
				from the host.
				For Multiword DMA transfers, the direction
				of data transfer is controlled by -IORD and
				-IOWR. This signal is used in a handshake
				manner with -DMACK (i.e., the device waits
				until the host asserts (-)DMACK before
				negating (-)DMARQ, and reasserts
				(-)DMARQ if there is more data to transfer).
				In PCMCIA I/O mode, the -DMARQ is
				ignored by the host while the host is
				performing an I/O Read cycle to the device.
				The host does not initiate an I/O Read cycle
				while -DMARQ is asserted by the device.
				In True IDE mode, DMARQ is not driven
				when the device is not selected in the
				Drive-Head register.
				While a DMA operation is in progress, -CS0
				(-CE1) and -CS1 (-CE2) are held negated
				and the width of the transfers is 16 bits.
				If there is no hardware support for True IDE
				DMA mode in the host, this output signal is
				not used and should not be connected at
				the host. In this case, the BIOS must report
				that DMA mode is not supported by the
				host so that device drivers do not attempt
				the DMA mode operation.
	GND	2, 19, 22,	-	Ground. The device ground signal.
		24, 26,
		30, 40,
		43
	INTRQ	31	O	Interrupt Request. This signal is an active
				high interrupt request to the host.

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4300D-00DSR PAGE 9 FEBRUARY 27, 2009