Silicon Image SSD-D32G(I)-4300 manual True IDE PIO Mode Read/Write Access Timing

ELECTRICAL SPECIFICATION SSD-DXXX(I)-4300 DATA SHEET

AC CHARACTERISTICS

True IDE PIO Mode Read/Write Access Timing

t0

ADDR valid
(A02, A01, A00, -CS0, -CS1)
(See note 1)	t1		t2	t9	t8
-IORD / -IOWR				t2i
Write
Data (D15:D00)
(See note 2)
			t3	t4
Read
Data (D15:D00)
(See note 2)
	t7		t5	t6
				t6z
-IOCS16
(See note 3)
IORDY
(See note 4a)		tA
IORDY
(See note 4b)		tC
			t RD
IORDY
(See note 4c)
			tB	tC

Figure 4: True IDE PIO Mode Read/Write Access Timing Diagram

Notes:

1.The device address consists of -CS0, -CS1, and A[02::00].

2.The data consists of D[15::00] (16-bit) or D[07::00] (8 bit).

3.-IOCS16 is shown for PIO modes 0, 1, and 2. For other modes, this signal is ignored.

4.The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of -IORD or -IOWR. The assertion and negation of IORDY is described in the following three cases:

a.The device never negates IORDY; no wait is generated.

b.The device starts to drive IORDY low before tA, but causes IORDY to be asserted before tA; no wait generated.

c.The device drives IORDY low before tA; wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and -IORD is asserted, the device places read data on D15- D00 for tRD before causing IORDY to be asserted.

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4300D-00DSR PAGE 13 FEBRUARY 27, 2009