ELECTRICAL SPECIFICATION

SSD-DXXX(I)-4300 DATA SHEET

DMARQ (device)

DMACK-

(host)

tLI tMLI

STOP (host)

tRP

DDMARDY-

(device)

tRFS

tLI

 

 

 

tMLI

 

 

HSTROBE

(host)

tDVS

DD(15:0)

tACK

tIORDYZ

tACK

tDVH

(host)

CRC

tACK

DA0, DA1, DA2,

CS0-, CS1-

Figure 15: Device Terminating a UDMA Data-Out Burst

Note: The definitions for the DIOW-:STOP, IORDY:DDMARDY- :DSTROBE, and DIOR-:HDMARDY-:HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.

Table 13: UDMA Data Burst Timing Requirements

Symbol

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Comment (see Notes 1 and

Units

 

 

 

 

 

 

 

 

 

 

Min. Max.

Min. Max.

Min. Max.

Min. Max.

Min. Max.

2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2CYCTYP

240

-

160

-

120

-

90

-

60

-

Typical sustained average

ns

 

 

 

 

 

 

 

 

 

 

 

two-cycle time.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

112

-

73

-

54

-

39

-

25

-

Cycle time allowing for

ns

 

 

 

 

 

 

 

 

 

 

 

asymmetry and clock

 

 

 

 

 

 

 

 

 

 

 

 

variations (from STROBE

 

 

 

 

 

 

 

 

 

 

 

 

edge to STROBE edge).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t2CYC

230

-

154

-

115

-

86

-

57

-

Two-cycle time allowing for

ns

 

 

 

 

 

 

 

 

 

 

 

clock variations (from rising

 

 

 

 

 

 

 

 

 

 

 

 

edge to next rising edge, or

 

 

 

 

 

 

 

 

 

 

 

 

from falling edge to next

 

 

 

 

 

 

 

 

 

 

 

 

falling edge of STROBE).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDS

15

 

10

 

7

 

7

 

5

 

Data setup time at recipient.

ns

tDH

5

-

5

-

5

-

5

-

5

-

Data hold time at recipient.

ns

SILICONSYSTEMS PROPRIETARY

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All unauthorized use and/or reproduction is prohibited.

4300D-00DSR

PAGE 24

FEBRUARY 27, 2009

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Silicon Image SSD-D32G(I)-4300 manual Device Terminating a Udma Data-Out Burst, Udma Data Burst Timing Requirements

SSD-D32G(I)-4300 specifications

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