Silicon Image SSD-D32G(I)-4300 manual Ultra DMA Data Burst Timing Requirements

Models: SSD-D32G(I)-4300

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Ultra DMA Data Burst Timing Requirements

ELECTRICAL SPECIFICATION

SSD-DXXX(I)-4300 DATA SHEET

Ultra DMA Data Burst Timing Requirements

The following figures and table describe the requirements for the Ultra DMA

(UDMA) data burst timing.

DMARQ (device)

tUI

DMACK-

(host)

tACK

STOP (host)

tENV

tFS

tZAD

HDMARDY-

(host)

tACKtENV

tZIORDY

tFS

tZAD

DSTROBE

(device)

tAZ

tDVS

DD(15:0)

tACK

DA0, DA1, DA2,

CS0-, CS1-

tDVH

Figure 6: Initiating a UDMA Data-In Burst

Note: The definitions for the DIOW-:STOP, DIOR-:HDMARDY-:HSTROBE, and IORDY:DDMARDY-:DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.

SILICONSYSTEMS PROPRIETARY

This document and the information contained within it is confidential and proprietary to SiliconSystems, Inc.

All unauthorized use and/or reproduction is prohibited.

4300D-00DSR

PAGE 17

FEBRUARY 27, 2009

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Silicon Image SSD-D32G(I)-4300 manual Ultra DMA Data Burst Timing Requirements, Initiating a UDMA Data-In Burst