Silicon Image SSD-D32G(I)-4300 manual Channel Ready. The signal is negated

ELECTRICAL SPECIFICATION				SSD-DXXX(I)-4300 DATA SHEET
		Table 8:	Signal Descriptions (Continued)
	Signal Name	Pin(s)	Type	Description
	IORDY	27	I	I/O Channel Ready. The signal is negated
	(True IDE			to extend the host transfer cycle of any host
	mode)			register access.
	-IORD	25	I	Device I/O Read. This is the read strobe
	(True IDE			signal from the host. The falling edge of
	mode)			IORD enables data from the device onto
				the data bus. The rising edge of IORD
				latches data at the host. The host does not
				act on the data until it is latched.
	-DDMARDY			When UDMA mode DMA write is active in
	(UDMA write			all modes, this signal is asserted by the
	protocol			device during a data burst to indicate that
	active)			the device is ready to receive UDMA data-
				out bursts.
				The device may negate -DDMARDY to
				pause a UDMA transfer.
	DSTROBE			When UDMA mode DMA read is active in
	(UDMA read			all modes, this signal is the data in strobe
	protocol			generated by the device. Both the rising
	active)			and falling edge of DSTROBE cause data
				to be latched by the host. The device may
				stop generating DSTROBE edges to pause
				a UDMA data-in burst.
	-IOWR	23	I	Device I/O Write. This is the write strobe
	(True IDE			signal from the host. The rising edge of
	mode)			IOWR# latches data from the data bit
				signals. The device does not act on the

data until it is latched.

-HDMARDY

(UDMA read protocol active)

When UDMA mode DMA read is active in all modes, this signal is asserted by the host to indicate that the host is ready to receive UDMA data-in bursts. The host may negate -HDMARDY to pause a UDMA transfer.

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4300D-00DSR PAGE 10 FEBRUARY 27, 2009