Chapter 1: Introduction
1-2 Chipset Overview
The Intel 3200 chipset, designed for use with an Intel Xeon 3000 sequence proces- sor in the LGA 775 Land Grid Array Package, is comprised of two primary com- ponents: the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH9R). The
Memory Controller Hub (MCH)
The function of the MCH is to manage the data fl ow between four interfaces: the CPU interface, the DDR2 System Memory interface, the PCI Express interface (Note 2), and the Direct Media Interface (DMI). The MCH is optimized for the Intel Xeon 3000 sequence processor in the LGA775 Land Grid Array package. It supports one or two channels of DDR2 SDRAM.
Intel ICH9R System Features
The I/O Controller (ICH9R) provides the data buffering and interface arbitration required for the system to operate effi ciently. It also provides the bandwidth needed for the system to maintain its peak performance. The Direct Media Interface (DMI) provides the connection between the MCH and the ICH9R. The ICH9R supports two
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Advanced Confi guration and Power Interface, Version 2.0 (ACPI)
Intel I/O External Design Specifi cation (EDS)
3200 Memory Controller Hub (MCH) External Design Specifi cation (EDS)
Intel I/O Controller Hub 9 (ICH9R ) Thermal Design Guideline
Intel 82573 Platform LAN Connect (PLC) PCI Design
Note 1: For more information on the ICH9R, please refer to Intel's website at
www.intel.com.
Note 2: The Intel 3200 chipset does not support