Chapter 1: Introduction

1-2 Chipset Overview

The Intel 3200 chipset, designed for use with an Intel Xeon 3000 sequence proces- sor in the LGA 775 Land Grid Array Package, is comprised of two primary com- ponents: the Memory Controller Hub (MCH) and the I/O Controller Hub (ICH9R). The X7SBL-LN1/LN2 provides the performance and feature-set required for the mainstream server market.

Memory Controller Hub (MCH)

The function of the MCH is to manage the data fl ow between four interfaces: the CPU interface, the DDR2 System Memory interface, the PCI Express interface (Note 2), and the Direct Media Interface (DMI). The MCH is optimized for the Intel Xeon 3000 sequence processor in the LGA775 Land Grid Array package. It supports one or two channels of DDR2 SDRAM.

Intel ICH9R System Features

The I/O Controller (ICH9R) provides the data buffering and interface arbitration required for the system to operate effi ciently. It also provides the bandwidth needed for the system to maintain its peak performance. The Direct Media Interface (DMI) provides the connection between the MCH and the ICH9R. The ICH9R supports two PCI-Express devices, six Serial ATA ports, and up to seven USB 2.0 ports/ headers. In addition, the ICH9R offers the Intel Matrix Storage Technology which provides various RAID options for data protection and rapid data access. It also supports the next generation of client management through the use of PROActive technology in conjunction with Intel's next generation Gigabit Ethernet controller. Functions and capabilities include:

Advanced Confi guration and Power Interface, Version 2.0 (ACPI)

Intel I/O External Design Specifi cation (EDS)

3200 Memory Controller Hub (MCH) External Design Specifi cation (EDS)

Intel I/O Controller Hub 9 (ICH9R ) Thermal Design Guideline

Intel 82573 Platform LAN Connect (PLC) PCI Design

Note 1: For more information on the ICH9R, please refer to Intel's website at

www.intel.com.

Note 2: The Intel 3200 chipset does not support add-in graphics cards in the PCI-E interface provided by the Memory Controller Hub (MCH)

1-9

Page 15
Image 15
SUPER MICRO Computer X7SBL-LN1/LN2 user manual Chipset Overview, Memory Controller Hub MCH, Intel ICH9R System Features