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Tyan Computer S8236 warranty Bit Data Transfer

Models: S8236

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32-Bit Data Transfer

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Tyan Computer S8236 warranty Bit Data Transfer

Contents

S8236 CopyrightTrademark Page Contents Check the box contents Before you begin…S8236WGM3NR 1.2 Hardware SpecificationsChapter 1 Instruction 1.1 CongratulationsS8236GM3NR Supported DIMM Qty 1.3 Software Specifications How to install our products right… the first time Chapter 2 Board Installation2.1 Board Image S8236 Block Diagram 2.2 Block Diagram2.3 Board Parts, Jumpers and Connectors Jumper Legend Jumpers & ConnectorsJumper/Connector FunctionState LED DefinitionsDescription SignalSignal DescriptionJ12 J56 J55 J30 J5 J54 J34 J4 J28 Fan TACH Connector J4 COM2 ConnectorJ5/J12/J30/J34/J54/J55/J56 4-Pin FAN Connectors J23 Front Panel ConnectorJ31 J29 LED1 J59 J59 IPMB Connector J29/J33 USB Front Panel ConnectorJ31 PSMI Connector J53 HDD Fault HeaderJP6 JP1 JP2JP7 JP7 Chassis Intrusion Header JP1/JP2 COM2 Function Switch JumperJP3 Clear CMOS Jumper JP6 Front Panel ID LED ButtonProcessor Installation G34 1944-pin Socket for AMD CPU 2.4 Installing the Processor and Heat sink4. Take off the CPU protection cap 3. Lift the socket cover to a fully open positionHeat sink Installation 2.5 Thermal Interface Material 2.6 Tips on Installing Motherboard in Chassis Page 2.7 Installing the Memory Recommended Memory Population Table Page DDR3 Rank U-DIMM Module SupportDDR3 Speed/Voltage DDR3 Speed/Voltage DDR3 Rank ConfigurationR-DIMM Module Support Memory Installation Procedure Attaching Serial ATA Cables 2.8 Attaching Drive Cables2.9 Installing Add-In Cards Left LED 2.10 Connecting External DevicesOnboard LAN LED Color Definition 10/100/1000 Mbps LAN Link/Activity LED Scheme 8-pin PW2, PW3 2.11 Installing the Power SupplyApplying power to the board 2.12 Finishing Up 3.1.1 Setup Basics Chapter 3 BIOS Setup3.1 About the BIOS To start the BIOS setup utility3.1.2 Getting Help 3.1.3 In Case of Problems3.1.4 Setup Variations Processor 3.2 Main MenuAMIBIOS System Time / Date setupSuper IO Configuration 3.3 Advanced MenuCPU Configuration IDE ConfigurationPowerNow 3.3.1 Advanced CPU ConfigurationGART Error Reporting Secure Virtual Machine ModeC1E Support Enable or disable the building of ACPI SRAT Table. Disabled / EnabledEnable or disable the C1 Enhanced mode. Disabled / Enabled ACPI SRAT TableHard Disk Write Protect 3.3.2 Advanced IDE ConfigurationDisabled / Enabled IDE Detect Time Out Sec Onboard PCI IDE Controller3.3.2.1 SATA0 Sub-Menu LBA/Large ModePIO Mode DMA Mode32-Bit Data Transfer Serial Port1 Address 3.3.3 Super I/O ConfigurationWatchdog Mode Watchdog TimerACPI APIC Support 3.3.4 ACPI Configuration3.3.4.1 Advanced ACPI Configuration ACPI Version FeaturesDisabled / Enabled Enabled / DisabledHeadless Mode Enable or disable Headless operation mode through ACPIAuto FAN Control 3.3.5 Hardware Health ConfigurationEnabled Fan speed according max temperature Enabled / Disabled Disabled3.5.1 Sensor Data Register Monitoring Read only. It can not be modified in user modeSet PEF Configuration 3.3.6 IPMI 2.0 ConfigurationSet LAN Configuration Set VLAN ConfigurationSEL Entry Number 3.3.6.2 Set LAN ConfigurationIP Address Configuration 3.3.6.1 View BMC System Event LogIP Address Source 3.3.6.2.1 Setup LAN ConfigurationSave LAN Configuration IP Address ConfigurationEnabled 3.3.6.3 Set VLAN ConfigurationSave VLAN ID Configuration Disabled / EnabledDisabled / Enabled Event Message For PEF Action 3.3.6.4 Set PEF ConfigurationAlert Startup Delay Disabled / Enabled Startup DelayRedirection After BIOS POST 3.3.7 Remote Access ConfigurationRemote Access Serial Port ModeVT-UTF8 Combo Key Support Sredir Memory Display DelayLegacy USB Support 3.3.8 USB ConfigurationUSB 2.0 Controller Mode BIOS EHCI Hand-OFFOnboard Lan3 3.3.9 Onboard Devices ConfigurationOnboard Lan1/Lan2 Onboard Lan1/Lan2 OP-ROMPlug & Play O/S 3.4 PCI/PnP MenuPCI Latency Timer Clear NVRAMPCI IDE Bus Master Quiet Boot Boot MenuBoot Settings Configuration Quick BootHit ‘DEL’ Message Display Boot Up Num-LockWait for ‘F1’ If Error Endless BootHard Disk Drives 3.5.2 Boot Device Priority1st Boot Device 3.5.3CD/DVD Drives 1st Boot Device3.5.4 CD/DVD Drives Change User Password 3.6 Security MenuSupervisor Password/User Password Change Supervisor Password NorthBridge Configuration 3.7 Chipset MenuAllow you to change NorthBridge, SouthBridge and RD890 Configuration Select which node’s timing parameters to display 3.7.1 North Bridge Configuration Memory Configuration Memory Timing ParametersBank Interleaving 3.7.1.1 Memory ConfigurationCS Sparing Enable Bank Swizzle ModeDRAM SCRUB REDIRECT 3.7.1.2 ECC ConfigurationECC Mode DRAM ECC EnableL2/L3 Cache BG Scrub DRAM Timing Config 3.7.1.3 DRAM Timing ConfigurationOHCI HC/EHCI HC 3.7.2 South Bridge ConfigurationSATA IDE Combined Mode Restore On AC Power LossSGPIO Function Disabled Disable Chassis Intrusion DetectionEnable or disable the SP5100 SGPIO function Enabled / Disabled Chassis Intrusion DetectionPrimary Video Controller 3.7.3 RD890 ConfigurationIOMMU  Port # 02 Features 3.7.3.1 PCI Express ConfigurationLink ASPM 3.7.3.1.1 Port # 02/03/11/12 FeaturesGen2 High Speed Mode Slot Power Limit, WLink ASPM 3.7.3.1.2 Port # 04/09/13 Features3.7.3.1.3 NB-SB Port Features DisabledEnabled 3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting3.7.3.1.4 SB Core Setting EnabledHT Link Tristate 3.7.3.2 Hyper Transport ConfigurationHT3 Link Power State HT Extended AddressSave Changes and Exit 3.8 Exit MenuLoad Optimal Defaults Load Failsafe DefaultsPage Memory, Video, CPU Chapter 4 Diagnostics4.1 Beep Codes 4.2 Flash Utility4.3 AMIBIOS Post Code 3A 3B 3C Page Glossary Page Firmware low-level software that controls the system hardware PCI Peripheral Component Interconnect a 32 or 64-bit local bus data pathway which is faster than the ISA bus. Local buses are those which operate within a single system as opposed to a network bus, which connects multiple systems RAIDIOS RAID I/O Steering Intel VGA Video Graphics Array the PC video display standard Help Resources Technical SupportReturning Merchandise for Service Notice for Canada Notice for the USAOperation is subject to the following conditions