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Tyan Computer S8236 Hyper Transport Configuration, HT Extended Address, HT3 Link Power State

Models: S8236

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3.7.3.2 Hyper Transport Configuration

		BIOS Setup Utility
Main	Advanced	PCI/PnP	Boot	Security	Chipset		Exit
Hyper Transport Configuration					Enabled: HT supports 52-bit
					physical addressing.
					physical addressing.
HT Extended Address					Disabled: HT supports 40-bit
HT Extended Address		[Disabled]			physical addressing.
HT3 Link Power State		[Auto]
HT Link Tristate		[Auto]			←	Select Screen
					↑↓ Select Item
					Enter Go to Sub Screen
					F1	General Help
					F10	Save and Exit
					ESC Exit

HT Extended Address

Enabled: HT supports 52-bit physical addressing.

Disabled: HT supports 40-bit physical addressing.

Disabled / Enabled / Auto

HT3 Link Power State

Select the HT3 Link Power State.

Auto / LS0 / LS1 / LS2 / LS3

HT Link Tristate

Select the HT1 Link Tristate mode.

Auto / Disabled / CAD/CTL / CAD/CTL/CLK

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Tyan Computer S8236 warranty Hyper Transport Configuration, HT Extended Address, HT3 Link Power State, HT Link Tristate

Contents

Trademark CopyrightS8236 Page Contents Before you begin… Check the box contents1.1 Congratulations 1.2 Hardware SpecificationsChapter 1 Instruction S8236WGM3NRS8236GM3NR Supported DIMM Qty 1.3 Software Specifications Chapter 2 Board Installation How to install our products right… the first time2.1 Board Image 2.2 Block Diagram S8236 Block Diagram2.3 Board Parts, Jumpers and Connectors Function Jumpers & ConnectorsJumper/Connector Jumper LegendLED Definitions StateDescription SignalSignal DescriptionJ12 J56 J55 J30 J5 J54 J34 J4 J23 Front Panel Connector J4 COM2 ConnectorJ5/J12/J30/J34/J54/J55/J56 4-Pin FAN Connectors J28 Fan TACH ConnectorJ31 J29 LED1 J59 J53 HDD Fault Header J29/J33 USB Front Panel ConnectorJ31 PSMI Connector J59 IPMB ConnectorJP6 JP1 JP2JP7 JP6 Front Panel ID LED Button JP1/JP2 COM2 Function Switch JumperJP3 Clear CMOS Jumper JP7 Chassis Intrusion Header2.4 Installing the Processor and Heat sink Processor Installation G34 1944-pin Socket for AMD CPU3. Lift the socket cover to a fully open position 4. Take off the CPU protection capHeat sink Installation 2.5 Thermal Interface Material 2.6 Tips on Installing Motherboard in Chassis Page 2.7 Installing the Memory Recommended Memory Population Table Page DDR3 Speed/Voltage U-DIMM Module SupportDDR3 Rank R-DIMM Module Support DDR3 Rank ConfigurationDDR3 Speed/Voltage Memory Installation Procedure 2.8 Attaching Drive Cables Attaching Serial ATA Cables2.9 Installing Add-In Cards 10/100/1000 Mbps LAN Link/Activity LED Scheme 2.10 Connecting External DevicesOnboard LAN LED Color Definition Left LEDApplying power to the board 2.11 Installing the Power Supply 8-pin PW2, PW3 2.12 Finishing Up To start the BIOS setup utility Chapter 3 BIOS Setup3.1 About the BIOS 3.1.1 Setup Basics3.1.4 Setup Variations 3.1.3 In Case of Problems3.1.2 Getting Help System Time / Date setup 3.2 Main MenuAMIBIOS ProcessorIDE Configuration 3.3 Advanced MenuCPU Configuration Super IO ConfigurationSecure Virtual Machine Mode 3.3.1 Advanced CPU ConfigurationGART Error Reporting PowerNowACPI SRAT Table Enable or disable the building of ACPI SRAT Table. Disabled / EnabledEnable or disable the C1 Enhanced mode. Disabled / Enabled C1E SupportOnboard PCI IDE Controller 3.3.2 Advanced IDE ConfigurationDisabled / Enabled IDE Detect Time Out Sec Hard Disk Write ProtectDMA Mode LBA/Large ModePIO Mode 3.3.2.1 SATA0 Sub-Menu32-Bit Data Transfer Watchdog Timer 3.3.3 Super I/O ConfigurationWatchdog Mode Serial Port1 AddressACPI Version Features 3.3.4 ACPI Configuration3.3.4.1 Advanced ACPI Configuration ACPI APIC SupportEnable or disable Headless operation mode through ACPI Enabled / DisabledHeadless Mode Disabled / EnabledDisabled 3.3.5 Hardware Health ConfigurationEnabled Fan speed according max temperature Enabled / Disabled Auto FAN ControlRead only. It can not be modified in user mode 3.5.1 Sensor Data Register MonitoringSet VLAN Configuration 3.3.6 IPMI 2.0 ConfigurationSet LAN Configuration Set PEF Configuration3.3.6.1 View BMC System Event Log 3.3.6.2 Set LAN ConfigurationIP Address Configuration SEL Entry NumberIP Address Configuration 3.3.6.2.1 Setup LAN ConfigurationSave LAN Configuration IP Address SourceDisabled / Enabled 3.3.6.3 Set VLAN ConfigurationSave VLAN ID Configuration EnabledDisabled / Enabled Startup Delay 3.3.6.4 Set PEF ConfigurationAlert Startup Delay Disabled / Enabled Event Message For PEF ActionSerial Port Mode 3.3.7 Remote Access ConfigurationRemote Access Redirection After BIOS POSTSredir Memory Display Delay VT-UTF8 Combo Key SupportBIOS EHCI Hand-OFF 3.3.8 USB ConfigurationUSB 2.0 Controller Mode Legacy USB SupportOnboard Lan1/Lan2 OP-ROM 3.3.9 Onboard Devices ConfigurationOnboard Lan1/Lan2 Onboard Lan3Clear NVRAM 3.4 PCI/PnP MenuPCI Latency Timer Plug & Play O/SPCI IDE Bus Master Quick Boot Boot MenuBoot Settings Configuration Quiet BootEndless Boot Boot Up Num-LockWait for ‘F1’ If Error Hit ‘DEL’ Message Display3.5.3 3.5.2 Boot Device Priority1st Boot Device Hard Disk Drives3.5.4 CD/DVD Drives 1st Boot DeviceCD/DVD Drives Change Supervisor Password 3.6 Security MenuSupervisor Password/User Password Change User PasswordAllow you to change NorthBridge, SouthBridge and RD890 Configuration 3.7 Chipset Menu NorthBridge Configuration Memory Timing Parameters 3.7.1 North Bridge Configuration Memory Configuration Select which node’s timing parameters to displayBank Swizzle Mode 3.7.1.1 Memory ConfigurationCS Sparing Enable Bank InterleavingDRAM ECC Enable 3.7.1.2 ECC ConfigurationECC Mode DRAM SCRUB REDIRECTL2/L3 Cache BG Scrub 3.7.1.3 DRAM Timing Configuration DRAM Timing ConfigRestore On AC Power Loss 3.7.2 South Bridge ConfigurationSATA IDE Combined Mode OHCI HC/EHCI HCChassis Intrusion Detection Disabled Disable Chassis Intrusion DetectionEnable or disable the SP5100 SGPIO function Enabled / Disabled SGPIO FunctionIOMMU 3.7.3 RD890 ConfigurationPrimary Video Controller 3.7.3.1 PCI Express Configuration  Port # 02 FeaturesSlot Power Limit, W 3.7.3.1.1 Port # 02/03/11/12 FeaturesGen2 High Speed Mode Link ASPMDisabled 3.7.3.1.2 Port # 04/09/13 Features3.7.3.1.3 NB-SB Port Features Link ASPMEnabled 3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting3.7.3.1.4 SB Core Setting EnabledHT Extended Address 3.7.3.2 Hyper Transport ConfigurationHT3 Link Power State HT Link TristateLoad Failsafe Defaults 3.8 Exit MenuLoad Optimal Defaults Save Changes and ExitPage 4.2 Flash Utility Chapter 4 Diagnostics4.1 Beep Codes Memory, Video, CPU4.3 AMIBIOS Post Code 3A 3B 3C Page Glossary Page Firmware low-level software that controls the system hardware PCI Peripheral Component Interconnect a 32 or 64-bit local bus data pathway which is faster than the ISA bus. Local buses are those which operate within a single system as opposed to a network bus, which connects multiple systems RAIDIOS RAID I/O Steering Intel VGA Video Graphics Array the PC video display standard Returning Merchandise for Service Technical SupportHelp Resources Operation is subject to the following conditions Notice for the USANotice for Canada