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Tyan Computer S8236 3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting, Turn Off PLL During L1/L23

Models: S8236

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3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting

	BIOS Setup Utility
Main Advanced	PCI/PnP Boot	Security	Chipset		Exit
Turn Off PLL During L1/L23	[Enabled]		Enabled
TXCLK Clock Gating in L1	[Enabled]		Disabled
LCLK Clock Gating in L1	[Enabled]			Select Screen
			←	Select Screen
			↑↓ Select Item
			Enter Go to Sub Screen
			F1	General Help
			F10	Save and Exit
			ESC Exit

Turn Off PLL During L1/L23

Enabled / Disabled

TXCLK Clock Gating in L1

Enabled / Disabled

LCLK Clock Gating in L1

Enabled / Disabled

3.7.3.1.4 SB Core Setting

	BIOS Setup Utility
Main Advanced	PCI/PnP Boot	Security	Chipset		Exit
TXCLK Clock Gating in L1	[Enabled]		Enabled
LCLK Clock Gating in L1	[Enabled]		Disabled
			←	Select Screen
			↑↓ Select Item
			Enter Go to Sub Screen
			F1	General Help
			F10	Save and Exit
			ESC Exit

TXCLK Clock Gating in L1

Enabled / Disabled

LCLK Clock Gating in L1

Enabled / Disabled

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Page 81

Image 81

Tyan Computer S8236 3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core Setting, Turn Off PLL During L1/L23, TXCLK Clock Gating in L1

Contents

Copyright TrademarkS8236 Page Contents Check the box contents Before you begin…Chapter 1 Instruction 1.2 Hardware Specifications1.1 Congratulations S8236WGM3NRS8236GM3NR Supported DIMM Qty 1.3 Software Specifications How to install our products right… the first time Chapter 2 Board Installation2.1 Board Image S8236 Block Diagram 2.2 Block Diagram2.3 Board Parts, Jumpers and Connectors Jumper/Connector Jumpers & ConnectorsFunction Jumper LegendState LED DefinitionsSignal SignalDescription DescriptionJ12 J56 J55 J30 J5 J54 J34 J4 J5/J12/J30/J34/J54/J55/J56 4-Pin FAN Connectors J4 COM2 ConnectorJ23 Front Panel Connector J28 Fan TACH ConnectorJ31 J29 LED1 J59 J31 PSMI Connector J29/J33 USB Front Panel ConnectorJ53 HDD Fault Header J59 IPMB ConnectorJP6 JP1 JP2JP7 JP3 Clear CMOS Jumper JP1/JP2 COM2 Function Switch JumperJP6 Front Panel ID LED Button JP7 Chassis Intrusion HeaderProcessor Installation G34 1944-pin Socket for AMD CPU 2.4 Installing the Processor and Heat sink4. Take off the CPU protection cap 3. Lift the socket cover to a fully open positionHeat sink Installation 2.5 Thermal Interface Material 2.6 Tips on Installing Motherboard in Chassis Page 2.7 Installing the Memory Recommended Memory Population Table Page U-DIMM Module Support DDR3 Speed/VoltageDDR3 Rank DDR3 Rank Configuration R-DIMM Module SupportDDR3 Speed/Voltage Memory Installation Procedure Attaching Serial ATA Cables 2.8 Attaching Drive Cables2.9 Installing Add-In Cards Onboard LAN LED Color Definition 2.10 Connecting External Devices10/100/1000 Mbps LAN Link/Activity LED Scheme Left LED2.11 Installing the Power Supply Applying power to the board 8-pin PW2, PW3 2.12 Finishing Up 3.1 About the BIOS Chapter 3 BIOS SetupTo start the BIOS setup utility 3.1.1 Setup Basics3.1.3 In Case of Problems 3.1.4 Setup Variations3.1.2 Getting Help AMIBIOS 3.2 Main MenuSystem Time / Date setup ProcessorCPU Configuration 3.3 Advanced MenuIDE Configuration Super IO ConfigurationGART Error Reporting 3.3.1 Advanced CPU ConfigurationSecure Virtual Machine Mode PowerNowEnable or disable the C1 Enhanced mode. Disabled / Enabled Enable or disable the building of ACPI SRAT Table. Disabled / EnabledACPI SRAT Table C1E SupportDisabled / Enabled IDE Detect Time Out Sec 3.3.2 Advanced IDE ConfigurationOnboard PCI IDE Controller Hard Disk Write ProtectPIO Mode LBA/Large ModeDMA Mode 3.3.2.1 SATA0 Sub-Menu32-Bit Data Transfer Watchdog Mode 3.3.3 Super I/O ConfigurationWatchdog Timer Serial Port1 Address3.3.4.1 Advanced ACPI Configuration 3.3.4 ACPI ConfigurationACPI Version Features ACPI APIC SupportHeadless Mode Enabled / DisabledEnable or disable Headless operation mode through ACPI Disabled / EnabledEnabled Fan speed according max temperature Enabled / Disabled 3.3.5 Hardware Health ConfigurationDisabled Auto FAN Control3.5.1 Sensor Data Register Monitoring Read only. It can not be modified in user modeSet LAN Configuration 3.3.6 IPMI 2.0 ConfigurationSet VLAN Configuration Set PEF ConfigurationIP Address Configuration 3.3.6.2 Set LAN Configuration3.3.6.1 View BMC System Event Log SEL Entry NumberSave LAN Configuration 3.3.6.2.1 Setup LAN ConfigurationIP Address Configuration IP Address SourceSave VLAN ID Configuration 3.3.6.3 Set VLAN ConfigurationDisabled / Enabled EnabledAlert Startup Delay 3.3.6.4 Set PEF ConfigurationDisabled / Enabled Startup Delay Disabled / Enabled Event Message For PEF ActionRemote Access 3.3.7 Remote Access ConfigurationSerial Port Mode Redirection After BIOS POSTVT-UTF8 Combo Key Support Sredir Memory Display DelayUSB 2.0 Controller Mode 3.3.8 USB ConfigurationBIOS EHCI Hand-OFF Legacy USB SupportOnboard Lan1/Lan2 3.3.9 Onboard Devices ConfigurationOnboard Lan1/Lan2 OP-ROM Onboard Lan3PCI Latency Timer 3.4 PCI/PnP MenuClear NVRAM Plug & Play O/SPCI IDE Bus Master Boot Settings Configuration Boot MenuQuick Boot Quiet BootWait for ‘F1’ If Error Boot Up Num-LockEndless Boot Hit ‘DEL’ Message Display1st Boot Device 3.5.2 Boot Device Priority3.5.3 Hard Disk Drives1st Boot Device 3.5.4 CD/DVD DrivesCD/DVD Drives Supervisor Password/User Password 3.6 Security MenuChange Supervisor Password Change User Password3.7 Chipset Menu Allow you to change NorthBridge, SouthBridge and RD890 Configuration NorthBridge Configuration  Memory Configuration 3.7.1 North Bridge ConfigurationMemory Timing Parameters Select which node’s timing parameters to displayCS Sparing Enable 3.7.1.1 Memory ConfigurationBank Swizzle Mode Bank InterleavingECC Mode 3.7.1.2 ECC ConfigurationDRAM ECC Enable DRAM SCRUB REDIRECTL2/L3 Cache BG Scrub DRAM Timing Config 3.7.1.3 DRAM Timing ConfigurationSATA IDE Combined Mode 3.7.2 South Bridge ConfigurationRestore On AC Power Loss OHCI HC/EHCI HCEnable or disable the SP5100 SGPIO function Enabled / Disabled Disabled Disable Chassis Intrusion DetectionChassis Intrusion Detection SGPIO Function3.7.3 RD890 Configuration IOMMUPrimary Video Controller  Port # 02 Features 3.7.3.1 PCI Express ConfigurationGen2 High Speed Mode 3.7.3.1.1 Port # 02/03/11/12 FeaturesSlot Power Limit, W Link ASPM3.7.3.1.3 NB-SB Port Features 3.7.3.1.2 Port # 04/09/13 FeaturesDisabled Link ASPM3.7.3.1.4 SB Core Setting 3.7.3.1.3 GPP1/GPP2/GPP3a/GPP3b Core SettingEnabled EnabledHT3 Link Power State 3.7.3.2 Hyper Transport ConfigurationHT Extended Address HT Link TristateLoad Optimal Defaults 3.8 Exit MenuLoad Failsafe Defaults Save Changes and ExitPage 4.1 Beep Codes Chapter 4 Diagnostics4.2 Flash Utility Memory, Video, CPU4.3 AMIBIOS Post Code 3A 3B 3C Page Glossary Page Firmware low-level software that controls the system hardware PCI Peripheral Component Interconnect a 32 or 64-bit local bus data pathway which is faster than the ISA bus. Local buses are those which operate within a single system as opposed to a network bus, which connects multiple systems RAIDIOS RAID I/O Steering Intel VGA Video Graphics Array the PC video display standard Technical Support Returning Merchandise for ServiceHelp Resources Notice for the USA Operation is subject to the following conditionsNotice for Canada