Directory and File Contents
<component_name>example design
The example design directory contains the example design files provided with the core. Table
Name | Description |
|
|
<project_dir>/<component_name>/example_design | |
|
|
<component_name>_top.ucf | Provides example constraints necessary for |
| processing the CAN core using the Xilinx |
| implementation tools. |
|
|
<component_name>_top.v[hd] | The VHDL or Verilog |
| example design; it instantiates the CAN core. |
|
|
<component_name>.v | |
| generated when Verilog design flow is |
| selected. |
|
|
Back to Top |
|
<component_name>/doc
The doc directory contains the PDF documentation provided with the core.
Table 4-4: Doc Directory
Name |
| Description |
|
|
|
| <project_dir>/<component_name>/doc | |
|
|
|
can_ds265.pdf |
| CAN v3.2 Data Sheet |
|
|
|
can_gsg186.pdf |
| CAN v3.2 Getting Started Guide |
|
|
|
Back to Top |
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CAN Getting Started Guide | www.xilinx.com | 19 |
UG186 April 19, 2010