Chapter 3: Quick Start Example Design
Functional Simulation
This section provides instructions for running a functional simulation of the CAN core using either VHDL or Verilog. Functional simulation models are provided when the core is generated. Implementing the core before simulating the functional models is not required.
To run a VHDL or Verilog functional simulation of the example design:
1.Set the current directory to:
<quickstart>/simulation/functional/
2.Launch the simulation script.
ModelSim: vsim
ncsim
ncsim
The simulation script compiles the functional simulation models and demonstration test bench, adds relevant signals to the wave window, and runs the simulation. To observe the operation of the core, inspect the simulation transcript and the waveform.
Timing Simulation
Timing simulation is supported only for the
To run a VHDL or Verilog functional simulation of the example design:
1.Set the current directory to:
<quickstart>/simulation/timing/
2.Launch the simulation script:
ModelSim: vsim
ncsim
ncsim
The simulation script compiles the timing simulation model and the demonstration test bench, adds relevant signals to the wave window, and runs the simulation. To observe the operation of the core, inspect the simulation transcript and the waveform.
16 | www.xilinx.com | CAN Getting Started Guide |
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| UG186 April 19, 2010 |