Xilinx UG018 ISOCM Controller Instruction Fetch Operation

144 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 3: PowerPC 405 OCM Controller
R
register defines the 16 MB memory region that is valid for the DSOCM. Load instructions
have a priority over store instructions at the DSOCM interface
Non-Memory Peripherals for DSOCM
The OCM interface is designed to connect to memory. To correctly implement non-
memory peripherals that attach to DSOCM, designers must be aw are of two OCM specific
behaviors: execution re-ordering and store-data bypass.
Execution Re-ordering
Under certain conditions, the OCM controller will change the order in which DSOCM
Load and Store instructions are executed. A Store access may be executed after a Load,
even though the Store is fetched before the Load by the processor. If maintained execution
order is necessary in the peripheral, the designer is responsible for enforcement. This can
be done in driver routines by issuing a dummy Store between the operations, or by adding
NOP padding between them. A hardware solution is to add a semaphore that flags the
completion of the Store operation.
Store-data Bypass
A Store followed immediately by a Load from the same address may be handled as an
internal operand forward in the OCM controller. This means that the data returned to the
processor as the result of the access isn’t taken from the data returned by the peripheral,
but rather from an internal OCM buffer. To ensure that the Load data is read from the
peripheral, the same techniques can be used as for execution reordering. Execution re-
ordering of accesses to the same address will only occur in combination with store-data
bypass, thus ensuring memory consistency.
ISOCM Controller Instruction Fetch Operation
The ISOCM controller accepts an address and associated control signals from the processor
during an instruction fetch cycle, and passes the valid address to the ISOCM interface.
Instructions stored in a BRAM can be loaded into it during FPGA device configuration.
Alternatively, the processor can load the ISOCM space using the ISINIT and ISFILL
registers on the DCR bus.
There are two datapaths from the processor block to access the instruction-side memory:
xThe main 64-bit, read only port for instruction fetch. Since this port is 64-bits wide,
two instructions will be fetched at once.
xThe secondary 32-bit port for memory initialization and software debug. For Virtex-II
Pro, this port is write only, so it has limited software debug capability. For Virtex-4,
this port supports both reads and writes and therefore has improved software debug
capabilities.