R

ChipScope PLBv46 IBA (Bus Analyzer) (v1.00a)

Table 2: IBA_PLBv46 Design Parameters (Continued)

Generic

Feature/Description

Parameter Name

Allowable Values

Default

VHDL

 

Value

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

G46

1=Enable storing MU 6 signals in the data

C_MU_6_EN_STORE_SLV_

0,1

1

Integer

 

 

sample storage buffer.

CTL_BUS

 

 

 

 

 

0=Disable

 

 

 

 

 

 

C_USE_MU_6A_SLV_CTL or

 

 

 

 

 

 

C_USE_MU_6B_SLV_SZ_WADDR must

 

 

 

 

 

 

be 1 in order to store.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave Busy Status

 

 

 

 

 

 

 

 

 

 

 

G47

USE SI_MBusy signal

C_USE_MU_7_SLV_BSY

1,0

0

Integer

 

 

 

 

 

 

 

 

G48

0=basic, 1=basic w/ edges

C_MU_7_TYPE_SLV_BSY

0,1

0

Integer

 

 

 

 

 

 

 

 

G49

Match unit counter width. 0 means do not

C_MU_7_CNT_W_SLV_BSY

0,1-32

0

Integer

 

 

use

 

 

 

 

 

 

 

 

 

 

 

 

G50

1=Enable storing MU 7 signals in the data

C_MU_7_EN_STORE_SLV_

0,1

1

Integer

 

 

sample storage buffer.

BSY

 

 

 

 

 

0=Disable

 

 

 

 

 

 

C_USE_MU_7_SLV_BSY must be 1 in

 

 

 

 

 

 

order to store.

 

 

 

 

 

 

 

 

 

 

 

 

 

Slave Read/Writer Error Status

 

 

 

 

 

 

 

 

 

 

 

G51

Use SI_MRdErr

C_USE_MU_8_SLV_RD_ERR

1,0

0

Integer

 

 

 

 

 

 

 

 

G52

0=basic, 1=basic w/ edges

C_MU_8_TYPE_SLV_RD_

0,1

0

Integer

 

 

 

ERR

 

 

 

 

 

 

 

 

 

 

 

G53

Match unit counter width. 0 means do not

C_MU_8_CNT_W_SLV_RD_

0,1-32

0

Integer

 

 

use

ERR

 

 

 

 

 

 

 

 

 

 

 

G54

1=Enable storing MU 8 signals in the data

C_MU_8_EN_STORE_SLV_

0,1

1

Integer

 

 

sample storage buffer.

RD_ERR

 

 

 

 

 

0=Disable

 

 

 

 

 

 

C_USE_MU_8_SLV_RD_ERR must be 1

 

 

 

 

 

 

in order to store.

 

 

 

 

 

 

 

 

 

 

 

 

G55

Use SI_MWrErr

C_USE_MU_9_SLV_WR_ERR

1,0

0

Integer

 

 

 

 

 

 

 

 

G56

0=basic, 1=basic w/ edges

C_MU_9_TYPE_SLV_WR_

0,1

0

Integer

 

 

 

ERR

 

 

 

 

 

 

 

 

 

 

 

G57

Match unit counter width. 0 means do not

C_MU_9_CNT_W_SLV_WR_

0,1-32

0

Integer

 

 

use

ERR

 

 

 

 

 

 

 

 

 

 

 

G58

1=Enable storing MU 9 signals in the data

C_MU_9_EN_STORE_SLV_

0,1

1

Integer

 

 

sample storage buffer.

WR_ERR

 

 

 

 

 

0=Disable

 

 

 

 

 

 

C_USE_MU_9_SLV_WR_ERR must be 1

 

 

 

 

 

 

in order to store.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLB Arbitration

 

 

 

 

 

 

 

 

 

 

 

G59

Use Master arbitration signals

C_USE_MU_10_ARB_CTL

1,0

0

Integer

 

 

 

 

 

 

 

 

G60

0=basic, 1=basic w/ edges

C_MU_10_TYPE_ARB_CTL

0,1

0

Integer

 

 

 

 

 

 

 

 

G61

Match unit counter width. 0 means do not

C_MU_10_CNT_W_ARB_CTL

0,1-32

0

Integer

 

 

use

 

 

 

 

 

 

 

 

 

 

 

 

G62

1=Enable storing MU 10 signals in the data

C_MU_10_EN_STORE_ARB_

0,1

1

Integer

 

 

sample storage buffer.

CTL

 

 

 

 

 

0=Disable

 

 

 

 

 

 

C_USE_MU_10_ARB_CTL must be 1 in

 

 

 

 

 

 

order to store.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DS619 (v1.0) September 17, 2007

www.xilinx.com

 

 

 

 

Product Specification

 

 

 

8

Page 8
Image 8
Xilinx v1.00a specifications Slave Busy Status, Slave Read/Writer Error Status, PLB Arbitration