MP3 NG: A Next Generation Consumer Platform

 

 

 

 

 

 

ROW-

 

ROW DECODER

 

 

BANK0

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

11

 

ADDRESS

 

 

2,048

 

 

 

 

 

 

 

 

 

 

ARRAY

 

 

 

 

 

 

 

 

 

LATCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(2,048 x 256 x 16)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CKE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

DQML,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQMH

CS#

 

COMMAND DECODE

CONTROL

 

 

 

 

 

 

 

256 (x16)

 

 

 

WE#

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CAS#

 

 

 

 

 

 

 

 

 

SENSE AMPLIFIERS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS#

 

 

 

 

 

 

 

 

 

I/O GATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQM MASK LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

 

 

 

MODE REGISTER

 

 

 

 

 

 

 

256

16

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

12

 

 

COLUMN- ADDRESS LATCH

BURST COUNTER

COLUMN-

ADDRESS BUFFER

 

 

 

 

DQ0-

 

 

 

 

 

 

 

COLUMN

 

16

 

 

 

 

 

 

 

 

DQ15

 

 

 

 

 

8

8

 

 

 

 

 

 

 

DECODER

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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INPUT8

 

 

 

 

 

 

 

 

 

 

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256

 

 

 

 

 

ADDRESS

REFRESH

 

 

 

 

 

 

 

 

 

 

 

A0-A10, BA

12

CONTROLLER

 

 

 

 

 

 

 

SENSE AMPLIFIERS

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O GATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQM MASK LOGIC

 

 

 

 

 

 

REFRESH

11

 

 

 

 

 

 

 

 

 

 

 

 

 

COUNTER

 

 

 

 

 

 

 

 

 

 

 

 

 

ROW-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS

 

 

 

 

 

 

256 (x16)

 

 

 

 

 

 

 

MUX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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ROW-

 

ROW DECODER

 

 

BANK1

 

 

 

 

 

 

 

 

 

 

 

 

MEMORY

 

 

 

 

 

 

 

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(2,048 x 256 x 16)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 10: MT48LC1M16A1 Block Diagram

(Courtesy of Micron Technology, Inc.)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

tCK

tCL

 

 

 

 

 

 

 

 

tCH

 

 

 

 

 

tCKS

tCKH

 

 

 

 

 

 

 

 

 

 

 

 

 

CKE

 

 

 

 

 

 

 

 

 

 

 

tCMS

tCMH

 

 

 

 

 

 

 

 

COMMAND

ACTIVE

NOP

READ

NOP

NOP

NOP

NOP

NOP

ACTIVE

 

 

 

 

tCMS tCMH

 

 

 

 

 

 

DQM3

 

 

 

 

 

 

 

 

 

 

 

tAS

tAH

 

 

 

 

 

 

 

 

A0-A9

ROW

 

COLUMN m

 

 

 

 

 

ROW

 

(A0 - A7)2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

tAH

 

ENABLE AUTO PRECHARGE

 

 

 

 

 

 

A10

ROW

 

 

 

 

 

 

 

ROW

 

tAS

tAH

 

 

 

 

 

 

 

 

BA

BANK

 

BANK

 

 

 

 

 

BANK

 

 

 

 

 

 

tAC

tAC

tAC

 

 

 

 

 

 

 

tAC

tOH

tOH

tOH

tOH

 

DQ

 

 

 

 

t LZ

DOUT m

DOUT m + 1

DOUT m + 2

DOUT m + 3

 

 

 

 

 

 

 

 

 

tHZ

 

 

 

 

 

 

 

 

 

 

 

 

 

tRCD

 

CAS Latency

 

 

tRP

 

 

 

 

tRAS

 

 

 

 

 

 

 

 

 

 

tRC

 

 

 

 

 

 

 

 

Figure 11: MT48LC1M16A1 Read Timing

(Courtesy of Micron Technology, Inc.)

R

10

www.xilinx.com

XAPP169 (v1.0) November 24, 1999

 

1-800-255-7778

 

Page 10
Image 10
Xilinx XAPP169 manual MT48LC1M16A1 Block Diagram

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.