MP3 NG: A Next Generation Consumer Platform

R

The only software support required for this block is the screen BIOS which consists of functions to generate screen images by manipulating the frame buffer memory. This buffer appears as an array of 512, 32-bit words with each word containing 32 pixels of the screen image. The most significant bit of the word at the base address appears as the pixel in the upper left-hand corner of the screen. The least significant bit of that memory word appears as the 32nd pixel in the first row. The word and bit address of any pixel on the screen can be calculated using the following formula:

Memory Address

= X * Y MOD 32

Bit Address

= X * Y REM 32

Where:

X and Y are the horizontal and vertical coordinates of the screen and

assume that the origin (X = 0, Y = 0) is in the upper left-hand corner of the screen. MOD the integer division.

REM is the remainder of the division

Memory Interface

The memory interface block, Figure 18 implements the data path required to map the 8- and 16-bit memory devices to the 32-bit IP bus. While the RC32364 is capable of fetching instruc- tions and data from devices with varying bus widths, having the FPGA build 32-bit words for the CPU reduces the number of bus cycles. This increases performance and also reduces power consumption. Figure 16 on page 16 shows a block diagram of this block.

A_IN[19:9]

A_IN[8:1]

MUX

A_IN[10:0]

MUX MEM_DOUT[15:8]

D_IN[31:24]

 

 

 

D_IN[23:16]

MUX MEM_DOUT[7:0]

D_IN[15:8]

D_IN[7:0]

 

 

 

 

Register

 

D_OUT[31:24]

 

 

MEM_DIN[15:8]

Q

D

MUX

 

 

Register

 

D_OUT[23:16]

Q

D

 

 

 

 

Register

 

D_OUT[15:8]

Q

D

 

 

MUX

 

 

D_OUT[7:0]

 

 

MEM_DIN[7:0]

MEM_ADDR[10:0]

MEM_D[15:0]

Figure 18: Memory Interface Block Diagram

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

19

 

1-800-255-7778

 

Page 18 Page 20
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Image 19
Xilinx XAPP169 manual Memory Interface Block Diagram
Page 18 Page 20

XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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