MP3 NG: A Next Generation Consumer Platform

R

Spartan Device Selection

Conclusion

Spartan devices are available in a range of densities and packages. The following criteria were used to select the device used in this application:

•I/O Pins. The design requires a total of 137 I/O pins. I/O pin requirements per block are summarized in FPGA Resource Usage Summary.

•Voltage. The design operates at 3.3V.

•Density. The estimated size of the design is 83,000 gates, with the usage broken out in Table 8.

•Performance. The highest clock speed used in the device is 64 MHz, used to clock the SDRAM controller state machines. The remaining logic runs at sub multiples of this clock rate.

•Packaging. The size constraints imposed on most modem designs dictates a high-density surface mount package.

Based on these criteria the device selected for this design is the XC2S100. This device offers 100K gates density, 3.3V operation, 176 user I/O, and is packaged in a space saving FG256 BGA package.

Table 8: FPGA Resource Usage Summary

Interface

CLB Usage

Number of Signals

 

 

 

 

 

CPU

25

51

 

 

 

 

 

LCD Display

58

9

 

 

 

 

 

IRDA

59

3

 

 

 

 

 

USB

21

3

 

 

 

 

 

DAC

23

5

 

 

 

 

 

ADC

0

3

 

 

 

 

 

SDRAM

100

9

 

 

 

 

 

FLASH

100

10

 

 

 

 

 

CompactFlash

100

17

 

 

 

 

 

Memory Address Bus

4

11

 

 

 

 

 

Memory Data Bus

10

16

 

 

 

 

 

Total:

500

137

 

 

 

 

 

 

 

 

 

The design that has been outlined meets both original design objectives. Even with budgetary pricing the cost of the solution is well below $100. Table 9 shows the cost breakdown of the system. The design also has enough spare resources both in terms of CPU cycles and FPGA gates to support field upgrades. Operating at a core clock speed of 64 MHz, the RC32364 will provide enough performance for both audio decoding and user interface functions. By locking the audio decode functions in the instruction cache a significant increase in system performance as well as reduced power consumption is achieved.

This design also illustrates how manufacturers can create designs that the optimized integration of an ASIC while supporting the manufacturing and field upgrade flexibility of an FPGA.

XAPP169 (v1.0) November 24, 1999

www.xilinx.com

25

 

1-800-255-7778

 

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Xilinx XAPP169 manual Conclusion, Spartan Device Selection, Total 500 137
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XAPP169 specifications

Xilinx XAPP169 is a pioneering application note that delves into the design and implementation of high-performance digital signal processing (DSP) systems. It serves as a reference guide for engineers and designers looking to leverage Xilinx Field Programmable Gate Arrays (FPGAs) for sophisticated DSP applications. The document provides a comprehensive overview of the techniques and methodologies necessary to harness the power and flexibility of FPGA technology in DSP design.

One of the main features of XAPP169 is its focus on the integration of various DSP functions, including filtering, modulation, and Fourier transforms. By utilizing the inherent parallelism of FPGAs, designers can achieve significant performance enhancements compared to traditional DSP implementations. This parallel processing capability allows for real-time processing of high-bandwidth signals, making XAPP169 ideal for applications such as telecommunications, aerospace, and medical imaging.

The application note emphasizes the use of Xilinx’s advanced tools and libraries, such as the Xilinx System Generator for DSP and the Xilinx Vivado Design Suite. These tools facilitate the modeling, simulation, and synthesis of DSP algorithms tailored to specific requirements, enabling a rapid development cycle. By providing pre-optimized building blocks and IP cores, XAPP169 streamlines the design process, reducing time-to-market for new products and innovations.

Additionally, XAPP169 highlights the ability to leverage high-speed serial transceivers present in Xilinx FPGAs. These transceivers enable reliable transmission of data across long distances with minimized latency and optimized bandwidth utilization. The application note outlines various techniques for managing signal integrity and maximizing throughput, ensuring that designs can meet the stringent requirements of modern DSP applications.

Another characteristic of XAPP169 is its attention to resource utilization and optimization strategies. The document discusses how to balance performance with area and power consumption, which is crucial in embedded applications where space and power are at a premium. By employing advanced synthesis strategies and leveraging the capabilities of Xilinx’s architecture, designers can create efficient and scalable DSP systems.

In summary, Xilinx XAPP169 serves as an invaluable resource for engineers seeking to harness the capabilities of FPGAs in DSP applications. With its focus on high-performance design, integration of advanced tools, and optimization strategies, it opens up new possibilities for innovation in various fields where digital signal processing is essential.
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