Xilinx XAPP169 manual RC32364 Block Diagram

MP3 NG: A Next Generation Consumer Platform

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The variable page size lets each mapping independently represent memory regions that can range from 4 KB to 16 MB. This feature lets the system designer adjust the address mapping granularity for different memory regions.

Locking TLB entries excludes entries from being recommended for replacement when there is an address miss. This lets the system designer have mappings for critical regions of code and or data locked into the TLB for predictable real time performance.

RISCore32300TM		MMU	RISCore4000 Compatible
Extended MIPS 32		w/	System Control
Integer CPU Core		TLB	Coprocessor (CPO)	Enhanced JTAG (ICE
8kB	I-Cache,		2kB D-Cache, 2-set,
2-set,	lockable			Interface)
			lockable, write-back/write-through
Clock		RISCore32300 Internal Bus Interface
Generation
Unit

RC32364 Bus Interface Unit

Figure 2: RC32364 Block Diagram

(Courtesy IDT)

Virtual Address with 1M (220) 4-Kbyte pages

39 32 31 29 28 20 bits = 1M 12 11 0

ASID

VPN

Offset

8 20 12

Bits 31, 30 and 29 of the virtual address select user, super- visor, or kernel address spaces.

				Virtual-to-physical-			Offset	passed
				translation in TLB			unchanged		to
		TLB		32-bit Physical Address			physical memory
31					0
				PFN	Offset
				Virtual-to-			Offset	pa ssed
			physical transla-
						unchanged to		physical
	TLB		tion in TLB
						memory.

39 32 31 29 28 24 23 0

ASID

VPN

Offset

8 8 24

8 bits = 256 pages

Virtual Address with 256 (28)16-Mbyte pages

Figure 3: RC32364 Address Translation

(Courtesy IDT)

4	www.xilinx.com	XAPP169 (v1.0) November 24, 1999
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