Xilinx XAPP169 Samsung FLASH Memory

8www.xilinx.com XAPP169 (v1.0) November 24, 1999

1-800-255-7778

MP3 NG: A Next Generation Consumer Platform R

Samsung

FLASH Memory The FLASH memory chosen for this design is the KM29U64000T 8M x 8 device from Samsung

Semiconductor. This device is based on NAND FLASH technology and is popular in MP3 player

applications due to its high density and low cost per bit.

Figure 8 shows the block diagram for this device. The complete data sheet for the

KM29U64000T can be found at the following URL:

http://www.usa.samsungsemi.com/products/prodspec/flash/km29u64000(i)t.pdf

Unfortunately this device also has two characteristics that prese nt significant system level

design challenges. The first of these is the narrow, highly multiplexed interface that is used to

access the device. The KM29U64000T interfaces to the system t hrough an 8-bit wide port that

is used for both address and data. Figure 9 illustrates the read timing for th is device.

The second and most challenging issue relates to data integrity, which is an issue common to

most devices using NAND technology. There are two aspects to this, the first of whic h is the fact

that devices when shipped may have memory blocks that may not be used due to data errors.

The data sheet for the device has a parameter called NVB that is the number valid bloc ks that

the device contains. The value of NVB varies from device to device an d is specified to have a

minimum of 1014, a maximum of 1024, and typically 1020. While the first bloc k is guaranteed

to be good, bad blocks can occur at any other location within the memory array. Invalid blocks

are marked at the factory by storing a "0" value at location "0" in either the first or second block

of the page. The system level impact of this is that it must keep trac k of which blocks are good

within the device and that this results in a non-contiguous memory map.

The second issue is that while the device is guaranteed to provide at l east the minimum number

of valid blocks over its operational lifetime these devices may ex perience failures in additional

blocks throughout their life. In order to ensure system integrity some form of error detection and

correction must be implemented.

The discussion of the FLASH memory interface will discuss ho w these issues were addressed

in this design.

X-Buffers

Y-Gating

64M + 2M Bit

Command

2nd half Page Register & S/A

NAND Flash

ARRAY

(512 + 16)Byte x 16384

Y-Gating

1st half Page Register & S/A

I/O Buffers & Latches

Latches

& Decoders

Y-Buffers

Latches

& Decoders

Control Logic

& High Voltage

Generator Global Buffers Output

Driver

A9 - A22

A0 - A7

Command

CLE ALE WP

I/0 0

I/0 7

VCCQ

VSS

Figure 8: KM29U64000T Block Diagram

(Courtesy Samsung Semiconductor)