YMF715E
8-1. Partial Power Down Mode
Functional blocks comprising
, blocks in the above diagram show those that can be disabled/enabled. Note, however, the
In this mode, master volume is not muted, so all analog input sources and enabled digital sources (i.e. FM, SB, WSS etc.) can be heard.
Note :
AUX2 inputs are exceptions in this regard since setting
8-2. Power Save Mode
SA3 control register, index 01h, PSV and PDX bits, implement these controls.
Clock generator can be controlled under either two options.
(i) Power Save Mode 1 (Clock Generator Control : Disabled (stop)) (PSV=PDX=1)
It is necessary to take some time before clock oscillation to stabilize. Power dissipation of digital portion becomes about 100uA(typ.), and that of analog portion becomes about 5mA(typ.).
(ii)Power Save Mode 2 (Clock Generator Control : Enabled (crystals keep on oscillating)) (PSV=1, PDX=0)
Leaving power save mode gets the
In these power save modes, the OUTL/R pins will keep the VREF voltage. During these modes, master volume is automatically muted, so all audio sources can not heard. After resuming from these modes, master volume is still muted.
(PDN=PDX=1)
This mode is to minimize power dissipation by stopping all the function of
VREF voltage slowly decays to ground on transition into this mode, and quickly returns to VREF on transition from this mode. During this mode, master volume is automatically muted, so all audio sources can not heard. After resuming from this mode, master volume is still muted.
May 21, 1997