YMF715E
AC Characteristics
CPU Interface & DMA BUS Cycle :Fig.1,2,3,4,5,6,7,8
Item | Symbol | Min. | Typ. | Max. | Unit |
/DACK inactive to /IOW, /IOR falling edge | tAKS | 50 |
|
| ns |
/DACK active from /IOW, /IOR rising edge | tAKH | 10 |
|
| ns |
Address set up to /IOW, /IOR active | tAS | 40 |
|
| ns |
Address hold to /IOW, /IOR inactive | tAH | 10 |
|
| ns |
/IOW Write Pulse Width | tWW | 90 |
|
| ns |
Write Data set up to /IOW active | tWDS | 20 |
|
| ns |
Write Data hold to /IOW inactive | tWDH | 10 |
|
| ns |
/IOR Read Pulse Width | tRW | 90 |
|
| ns |
Read Data access time | tACC |
|
| 80 | ns |
Read Data hold from /IOR inactive | tRDH | 0 |
|
| ns |
DRQ hold from /IOW, /IOR falling edge | tDGH | 0 |
| 20 | ns |
/DACK set up to /IOW, /IOR falling edge | tSF | 25 |
|
| ns |
/DACK hold to /IOW, /IOR rising edge | tHR | 25 |
|
| ns |
Time between rising edge of /IOW, /IOR to next |
|
|
|
|
|
falling edge of /IOW, /IOR | tNX | 100 |
|
| ns |
Valid Address from /SYNCS or /MCS | tEX1 |
|
| 70(90) * | ns |
/SYNCS or /MCS | tEX2 |
|
| 70(90) * | ns |
RESET Pulse Width | tRST | 90 |
|
| μ s |
Note : DVSS=AVSS=0[V], TOP=0~70℃, DVDD=5.0±0.25[V] or 3.3±0.30[V], AVDD=5.0[V] *... The value into the brackets is specified at DVDD=3.3±0.30[V].
Serial Audio (Zoomed Video) Interface Input :Fig.9
Item | Symbol | Condition | Min. | Typ. | Max. | Unit |
BCLK Cycle | fBCK |
| 32fs | 48fs | 64fs | kHz |
BCLK Duty | DBCLK |
| 40 | 50 | 60 | % |
LRCK Hold Time | tLRH | BCLK↑/LRCK |
| 120 | ns | |
SIN Set up Time | tDS | BCLK↑/SIN | 20 |
|
| ns |
SIN Hold Time | tDH | BCLK↑/SIN | 20 |
|
| ns |
CLKO Frequency | fCLKO33 |
|
| 33.8688 |
| MHz |
CLKO Duty | DCLKO33 | f33=50% | 40 | 50 | 60 | % |
Note : DVSS=AVSS=0[V], TOP=0~70℃, DVDD=5.0±0.25[V] or 3.3±0.30[V], AVDD=5.0[V]
Duty Search Point is 1/2 DVDD.
May 21, 1997