Yamaha OPL3-SA3 specifications YMF715E, Digital Block Partial Power Down R/W

MPU...

MCLKO

FM...

WSS_R...

WSS_P...

SB...

PnP...

default : 00h

YMF715E

Digital Block Partial Power Down (R/W):

Index	D7	D6	D5	D4	D3	D2	D1	D0
12h	JOY	MPU	MCLKO	FM	WSS_R	WSS_P	SB	PnP

This register specifies the partial power management of the digital portion. This function is to spare power dissipation in unneeded blocks.

JOY... Setting this bit to “1” makes the Joystick portion in power down mode. Note that the Joystick portion must be re-initialized by writing any value to the Joystick port after resuming from the Joystick portion power down mode.

Setting this bit to “1” makes the MPU401 portion in power down mode. when set to “1”, Master Clock(33.8688MHz) is disable, which appears on the pin MP9(SEL=1,3,4,7).

when set to “0”, normal operation is active.

Setting this bit to “1” makes the internal FM(OPL3) portion in power down mode.

Setting this bit to “1” makes the WSS recording portion in power down mode.

Setting this bit to “1” makes the WSS playback portion and the digital loopback portion in power down mode.

Setting this bit to “1” makes the Sound Blaster compatible portion in power down mode.

Setting this bit to “1” makes the PnP portion in power down mode.

Analog Block Partial Power Down (R/W):

Index	D7	D6	D5	D4	D3	D2	D1	D0
13h	-	-	-	FMDAC	A/D	D/A	SBDAC	WIDE

This register specifies the partial power management of the analog portion. The respective outputs of the blocks which are to be disabled should be muted beforehand.

FMDAC...	Setting this bit to “1” makes the FMDAC portion for the internal FM(OPL3)
	or external synthesizer(OPL4-ML/ML2) or ZV port etc. in power down
	mode. AUX2 should be muted via register before setting the FMDAC
	portion to power down.
A/D...	Setting this bit to “1” makes the A/D portion for the WSS recording in
	power down mode.
D/A...	Setting this bit to “1” makes the D/A portion for the WSS playback in power
	down mode. WSS CODEC indirect register, index 06h and 07h, LOM and
	ROM bits must be “1”, before doing this.
SBDAC...	Setting this bit to “1” makes the SBDAC portion in power down mode. SB
	master volume should be muted via register before setting the SBDAC
	portion to power down.
WIDE...	Setting this bit to “1” makes the Wide Stereo(3D Enhanced Control) portion
	in power down mode. The 3D Enhanced parameter registers at index 14, 15,
	and 16h must be 00h, when doing this.
default : 00h

May 21, 1997

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