YMF724F

4-4. AC-2 / AC3F2 Master Clock (Fig.5)

Item

Symbol

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

CMCLK Cycle Time

tCMCYC

-

40.69

-

ns

CMCLK High Time

tCMHIGH

8

-

-

ns

CMCLK Low Time

tCMLOW

8

 

-

ns

CMCLK Rising Time

tCMR

-

4.6

-

ns

CMCLK Falling Time

tCMF

-

2.1

-

ns

Note : Top = 0-70°C, PVDD=5.0 ±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF

t CMR

t CMF

 

3.5 V

CMCLK

2.5 V

 

 

1.0 V

t CMHIGH t CMLOW

t CMCYC

Fig.5: Master Clock timing for AC-2 and AC3F2

4-5. AC-link (Fig.6)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

CBCLK Cycle Time

tCBICYC

 

-

81.4

-

ns

CBCLK High Time

tCBIHIGH

 

35

40.7

45

ns

CBCLK Low Time

tCBILOW

 

35

40.7

45

ns

CSYNC Cycle Time

tCSYCYC

 

-

20.8

-

ns

CSYNC High Time

tCSYHIGH

 

-

1.3

-

ns

CSYNC Low Time

tCSYLOW

 

-

19.5

-

ns

CBCLK to Signal Valid Delay

tCVAL

*12

-

-

20

ns

Output Hold Time for CBCLK

tCOH

*12

0

-

-

ns

Input Setup Time to CBCLK

tCISU

*13

15

-

-

ns

Input Hold Time for CBCLK

tCIH

*13

5

-

-

ns

Note) Top = 0-70°C, PVDD=5.0 ±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF *12: This characteristic is applicable to CSYNC and CSDO signal.

*13: This characteristic is applicable to CSDI signal.

September 21, 1998

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Yamaha YMF724F specifications AC-2 / AC3F2 Master Clock, AC-link