YMF724F
September 21, 1998
-44-
4. AC Characteristics
4-1. Master Clock (Fig.1)
Item Symbol Min. Typ. Max. Unit
XI24 Cycle Time tXICYC - 40.69 - ns
XI24 High Time tXIHIGH 16 - 24 ns
XI24 Low Time tXILOW 16 - 24 ns
Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V
t
XI24
XICYC
t
XIHIGH
1.0 V
2.5 V
3.5 V
t
XILOW
Fig.1: XI24 Master Clock timing
4-2. Reset (Fig.2)
Item Symbol Min. Typ. Max. Unit
Reset Active Time after Power Stable tRST 1--ms
Power Stable to Reset Rising Edge tRSTOFF 10 - - ms
Reset Slew Rate - 50 - - mV/ns
Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V, CL=50 pF
PVDD, VDD5
RST#
VDD3
4.75 V
3.0 V
0.8 V
t
RST
t
RSTOFF
Fig.2: PCI Reset timing