Cypress SL811HS

SL811HS

Document 38-08008 Rev. *D Page 4 of 32

“SL811HS Slave Mode Registers” on page12 describes Slave

microprocessor interface similar to normal RAM accesses

(see “Bus Interface Timing Requirements” on page 26) and

provide control and status information for USB transactions.

Any write to control register 0FH enables the SL811HS full

features bit. This is an internal bit of the SL811HS that enables

additional features.

Tabl e 1 shows the memory map and register mapping of the

SL811HS in master/host mode.

SL811HS Master (Host) Mode Registers

The registers in the SL811HS are divided into two major

groups. The first group is referred to as USB Control registers.

These registers enable and provide status for control of USB

transactions and data flow. The second group of registers

provides control and status for all other operations.

The following registers initialize to zero on power up and reset:

• USB-A/USB-B Host Control Register [00H, 08H] bit 0 only

• Control Register 1 [05H]

• USB Address Register [07H]

• Current Data Set/Hardware Revision/SOF Counter LOW

All other register’s power up and reset in an unknown state and

firmware for initialization.

USB Control Registers

Communication and data flow on the USB bus uses the

SL811HS’ USB A-B Control registers. The SL811HS commu-

nicates with any USB Device function and any specific

endpoint via the USB-A or USB-B register sets.

The USB A-B Host Control registers are used in an overlapped

configuration to manage traffic on the USB bus. The USB Host

Control register also provides a means to interrupt an external

CPU or microcontroller when one of the USB protocol transac-

tions is completed. Tabl e 1 and Table2 show the two sets of

USB Host Control registers, the ’A’ set and ’B’ set. The two

parameters is being set up, the other is transferring. On

completion of a transfer to an endpoint, the next operation is

controlled by the other register set.

Note The USB-B register set is used only when SL811HS

mode is enabled by initializing register 0FH.

The SL811HS USB Host Control has two groups of five

registers each which map in the SL811HS memory space.

These registers are defined in the following tables.

SL811HS Host Control Registers.

Table 1. SL811HS Master (Host) Register Summary

SL811HS SL811HS

(hex) Address

USB-A Host Control Register 00h

USB-A Host Base Address 01h

USB-A Host Base Length 02h

USB-A Host PID, Device Endpoint

(Write)/USB Status (Read) 03h

USB-A Host Device Address (Write)/Transfer

Count (Read) 04h

Control Register 1 05h

Interrupt Enable Register 06h

Reserved Register Reserved

USB-B Host Control Register 08h

USB-B Host Base Address 09h

USB-B Host Base Length 0Ah

USB-B Host PID, Device Endpoint

(Write)/USB Status (Read) 0Bh

USB-B Host Device Address (Write)/Transfer

Count (Read) 0Ch

Status Register 0Dh

SOF Counter LOW (Write)/HW Revision Reg-

ister (Read) 0Eh

SOF Counter HIGH and Control Register 2 0Fh

Memory Buffer 10H-FFh

Table 2. SL811HS Host Control Registers