Package Markings 28-pin Plcc | Cypress SL811HS guide

SL811HS

The diagram below illustrates a simple +3.3V voltage source.

Figure 5. Sample VDD Generator

+5V (USB)

45 Ohms

2N2222

Zener

3.9v, 1N52288CT-

GND

+3.3 V (VDD)

Sample VDD Generator

Package Markings (28-pin PLCC)

Part Number

YYWW-X.X

XXXX

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

Document 38-08008 Rev. *D

Page 19 of 32

Page 19

Image 19

Cypress SL811HS manual Diagram below illustrates a simple +3.3V voltage source, Package Markings 28-pin Plcc

Contents

Cypress Semiconductor Corporation FeaturesIntroduction Master/Slave Controller Interrupt Controller DMA Controller slave mode onlyAuto Address Increment Mode Data Port, Microprocessor Interface USB Transceiver SL811HS RegistersMHz Crystals Frequency Tolerance USB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 D7-D4 HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 PID Type DA7 HTC7HTC2 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Control Register 1 Address 05h Bits 3 Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h Bit USB-B Done Interrupt Enable Register Address 06hUSB-B USB-A Done Revision Reserved Bit Position Bit Name Function Interrupt Status Register Address 0Dh BitValue of the Data+ pin USB-B SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register Addresses EPxLEN1 EPxLEN0 Endpoint Control RegistersSequence Next Data Set Control Register 0Fh SOF Low Byte Register Reserved OverflowTransmission Acknowledge Current Data Set Register Stbyd Spsel Control Register 1 Address 05hStbyd Interrupt Status Register Address 0Dh USB Address Register, Address 07h. This registerUSB Address Register Address 07h USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 SL811HS Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit Reserved Master/Slave Pin Plcc Pin Layout Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Physical Connections Package Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage source Pin Tqfp AXC Pin Layout Pin Tqfp Physical Connections Power for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins Description Buffer or register Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Data 7. Microprocessor Data/Address Bus Package Markings 48-Pin Tqfp Yyww Xxxx Electrical Specifications DC Characteristics Parameter Description Min Typ Max NWR High Bus Interface Timing RequirementsWrite Cycle Parameter Description Min Typ Max Read Cycle DMA Write Cycle DMA Write Cycle NRst High to nRD or nWR active Reset TimingDMA Read Cycle NRst Pulse width Part Number Package Type Package DiagramsOrdering Information CLOCKClock TimingTIMING Parameter Description Min Typ Max Lead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no