Cypress SL811HS

SL811HS

Document 38-08008 Rev. *D Page 19 of 32

The diagram below illustrates a simple +3.3V voltage source.

Package Markings (28-pin PLCC)

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

+5V ( US B )

GND

+3.3 V (VDD)

Sample VDD Generator

45 Ohms

3.9v, 1N52288CT-

Zener

2N2222

Figure 5. Sample VDD Generator

Part Number

YYWW-X.X

XXXX

Contents

Main SL811HS Embedded USB Host/Slave Controller SL811HS Features Block Diagram Introduction Page SL811HS Registers Page Page Page Page Page Page Page SL811HS Page Page Page Page Page Page Document 38-08008 Rev. *D Page 18 of 32 Physical Connections Figure 4. 28-pin PLCC USB Host/Slave Controller Pin Layout 28 PLCC 28-Pin PLCC Mechanical Dimensions Page Document 38-08008 Rev. *D Page 20 of 32 48-Pin TQFP Physical Connections 48-Pin TQFP AXC Pin Layout NC 12 48-Pin TQFP Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout Page Page Page Electrical Specifications Page nWR A0 D0-D7 DATA nCS I/O Write Cycle to R e g is te r o r Memory Buffer nRD A0 D0-D7 DATA nCS I/O Read Cycle from Register or Mem o ry Buffer nWR DMA Write Cycle nDRQ nDACK D0-D7 DATA nRD SL811 DMA READ C YC LE TIMING nRST SL811 DMA Read Cycle Timing treset nRD or nWR Reset Timing Ordering Information CLK CLOCK TIMING Package Diagrams Document History Page