Cypress SL811HS DMA Write Cycle

SL811HS

Document 38-08008 Rev. *D Page 28 of 32

DMA Write Cycle

Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the

next nDRQ is not inserted.

Parameter Description Min. Typ. Max.

tdack nDACK low 80 ns

tdwrlo nDACK to nWR low delay 5 ns

tdakrq nDACK low to nDRQ high delay 5 ns

tdwrp nWR pulse width 65 ns

tdhld Data hold after nWR high 5 ns

tdsu Data set-up to nWR strobe low 60 ns

tackrq NDACK high to nDRQ low 5 ns

tackwrh NDACK high to nDRQ low 5 ns

twrcycle DMA Write Cycle Time 150 ns

nDRQ

nDACK

D0-D7 DATA

nWR

SL811 DMA WR ITE CYC LE TIMING

tdwrp

tdsu

tdack

tdhld

tdwrlo

tackwrh

tdakrq tackrq

DMA Write Cycle

Contents

Main SL811HS Embedded USB Host/Slave Controller SL811HS Features Block Diagram Introduction Page SL811HS Registers Page Page Page Page Page Page Page SL811HS Page Page Page Page Page Page Document 38-08008 Rev. *D Page 18 of 32 Physical Connections Figure 4. 28-pin PLCC USB Host/Slave Controller Pin Layout 28 PLCC 28-Pin PLCC Mechanical Dimensions Page Document 38-08008 Rev. *D Page 20 of 32 48-Pin TQFP Physical Connections 48-Pin TQFP AXC Pin Layout NC 12 48-Pin TQFP Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout Page Page Page Electrical Specifications Page nWR A0 D0-D7 DATA nCS I/O Write Cycle to R e g is te r o r Memory Buffer nRD A0 D0-D7 DATA nCS I/O Read Cycle from Register or Mem o ry Buffer nWR DMA Write Cycle nDRQ nDACK D0-D7 DATA nRD SL811 DMA READ C YC LE TIMING nRST SL811 DMA Read Cycle Timing treset nRD or nWR Reset Timing Ordering Information CLK CLOCK TIMING Package Diagrams Document History Page