DMA Write Cycle

SL811HS

nDRQ

nDACK

tdakrqtackrq

tdack

tdwrlo

D0-D7		DATA
	tdsu	tdwrp

nW R

DMA Write Cycle

SL811 DMA W RITE CYCLE TIMING

tdhld

tackwrh

Parameter	Description	Min.	Typ.	Max.

tdack	nDACK low	80 ns

tdwrlo	nDACK to nWR low delay	5 ns

tdakrq	nDACK low to nDRQ high delay	5 ns

tdwrp	nWR pulse width	65 ns

tdhld	Data hold after nWR high	5 ns

tdsu	Data set-up to nWR strobe low	60 ns

tackrq	NDACK high to nDRQ low	5 ns

tackwrh	NDACK high to nDRQ low	5 ns

twrcycle	DMA Write Cycle Time	150 ns

Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next nDRQ is not inserted.

Document 38-08008 Rev. *D

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Contents

Features IntroductionMaster/Slave Controller Cypress Semiconductor Corporation DMA Controller slave mode only Auto Address Increment ModeData Port, Microprocessor Interface Interrupt Controller SL811HS Registers MHz CrystalsFrequency Tolerance USB Transceiver USB Control Registers Register Values on Power Up and ResetSL811HS Host Control Registers Bit Position Bit Name Function ISOHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL7 HBL6 HBL4 HBL3 HBL2 HBL1 HBL0PID Type D7-D4 HTC7 HTC2DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 Low-power Modes Bit 6 Control Register, Address 05h USB Reset SequenceControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3 Interrupt Enable Register Address 06h USB-B USB-ADone USB-B Done Interrupt Status Register Address 0Dh Bit Value of the Data+ pinUSB-B Revision Reserved Bit Position Bit Name Function SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Register Name Miscellaneous register addresses Endpoint RegistersEndpoints 0-3 Register Addresses Endpoints 0-3 Register Addresses Endpoint Control Registers SequenceNext Data Set EPxLEN1 EPxLEN0 Reserved Overflow Transmission AcknowledgeCurrent Data Set Register Control Register 0Fh SOF Low Byte Register Stbyd Spsel Control Register 1 Address 05hStbyd USB Address Register, Address 07h. This register USB Address Register Address 07hUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0Dh Current Data Set Register Address 0Eh Control Register 2 Address 0Fh BitReserved Master/Slave SL811HS Pin Plcc Mechanical Dimensions Physical ConnectionsPin Plcc Physical Connections Pin Plcc Pin Layout Diagram below illustrates a simple +3.3V voltage source Package Markings 28-pin Plcc Pin Tqfp Physical Connections Pin Tqfp AXC Pin Layout 48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DD Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master Data 6. Microprocessor Data/Address BusData 7. Microprocessor Data/Address Bus Buffer or register Yyww Xxxx Package Markings 48-Pin Tqfp Electrical Specifications DC Characteristics Parameter Description Min Typ Max Bus Interface Timing Requirements Write CycleParameter Description Min Typ Max NWR High Read Cycle DMA Write Cycle DMA Write Cycle Reset Timing DMA Read CycleNRst Pulse width NRst High to nRD or nWR active Package Diagrams Ordering InformationCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package Type Lead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Document History Issue Date Orig. Description of ChangeREV ECN no

Cypress SL811HS manual DMA Write Cycle

Models: SL811HS

DMA Write Cycle

DMA Write Cycle

SL811 DMA W RITE CYCLE TIMING

Parameter