Electrical Specifications | Cypress SL811HS guide

SL811HS

Electrical Specifications

Absolute Maximum Ratings

This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability.

Description					Condition
Storage Temperature		–40°C to 125°C

Voltage on any pin with respect to ground		–0.3V to 6.0V

Power Supply Voltage (VDD)		4.0V
Power Supply Voltage (VDD1)		4.0V
Lead Temperature (10 seconds)		180°C

Recommended Operating Condition

Parameter	Min.			Typical		Max.
Power Supply Voltage, VDD	3.0V			3.3V		3.45V

Power Supply Voltage, VDD1	3.0V					3.45V

Operating Temperature	0°C					65°C


Crystal Requirements,	Min.			Typical		Max.
(X1, X2)	Min.			Typical		Max.
(X1, X2)
Operating Temperature Range	0°C					65°C

Parallel Resonant Frequency[10]				48 MHz
Frequency Drift over Temperature						±50 ppm
Accuracy of Adjustment						±30 ppm
Series Resistance						100 Ohms
Shunt Capacitance	3 pF					6 pF

Load Capacitance				20 pF
Drive Level	20 μW					5 mW

Mode of Vibration Third Overtone[11]
External Clock Input Characteristics (X1)

Parameter	Min.			Typical		Max.
Clock Input Voltage @ X1 (X2 Open)	1.5V

Clock Frequency[12]				48 MHz

Notes

10.The 28-PIN plcc can use a 12 MHz Crystal Oscillator or 12 MHz Clock Source.

11.Fundamental mode for 12 MHz Crystal.

12.The SL811HS can use a 12 MHz Clock Source.

Document 38-08008 Rev. *D

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Cypress SL811HS manual Electrical Specifications

Contents

Features IntroductionMaster/Slave Controller Cypress Semiconductor Corporation DMA Controller slave mode only Auto Address Increment ModeData Port, Microprocessor Interface Interrupt Controller SL811HS Registers MHz CrystalsFrequency Tolerance USB Transceiver Register Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 HBL7 HBL6 HBL4 HBL3 HBL2 HBL1 HBL0PID Type D7-D4 HTC7 HTC2DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 Low-power Modes Bit 6 Control Register, Address 05h USB Reset SequenceControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3 Interrupt Enable Register Address 06h USB-B USB-ADone USB-B Done Interrupt Status Register Address 0Dh Bit Value of the Data+ pinUSB-B Revision Reserved Bit Position Bit Name Function SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Register Name Miscellaneous register addresses Endpoint RegistersEndpoints 0-3 Register Addresses Endpoints 0-3 Register Addresses Endpoint Control Registers SequenceNext Data Set EPxLEN1 EPxLEN0 Reserved Overflow Transmission AcknowledgeCurrent Data Set Register Control Register 0Fh SOF Low Byte Register Control Register 1 Address 05h Stbyd SpselStbyd USB Address Register, Address 07h. This register USB Address Register Address 07hUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0Dh Current Data Set Register Address 0Eh Control Register 2 Address 0Fh BitReserved Master/Slave SL811HS Pin Plcc Mechanical Dimensions Physical ConnectionsPin Plcc Physical Connections Pin Plcc Pin Layout Diagram below illustrates a simple +3.3V voltage source Package Markings 28-pin Plcc Pin Tqfp Physical Connections Pin Tqfp AXC Pin Layout 48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DD Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master Data 6. Microprocessor Data/Address BusData 7. Microprocessor Data/Address Bus Buffer or register Yyww Xxxx Package Markings 48-Pin Tqfp Electrical Specifications DC Characteristics Parameter Description Min Typ Max Bus Interface Timing Requirements Write CycleParameter Description Min Typ Max NWR High Read Cycle DMA Write Cycle DMA Write Cycle Reset Timing DMA Read CycleNRst Pulse width NRst High to nRD or nWR active Package Diagrams Ordering InformationCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package Type Lead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no