DMA Read Cycle, Reset Timing, NRst Pulse width

SL811HS

DMA Read Cycle

nDRQ

tdckdr

nDACK

tdack

D0-D7

tddrdlo

DATA

tdaccs

nRD

tdrdp

SL811 DMA Read Cycle Timing

SL811 DMA READ CYCLE TIMING

tdakrq

tdhld

Parameter	Description	Min.	Typ.	Max.

tdack	nDACK low	100 ns

tddrdlo	nDACK to nRD low delay	0 ns

tdckdr	nDACK low to nDRQ high delay	5 ns

tdrdp	nRD pulse width	90 ns

tdhld	Date hold after nDACK high	5 ns

tddaccs	Data access from nDACK low	85 ns

tdrdack	nRD high to nDACK high	0 ns

tdakrq	nDRQ low after nDACK high	5 ns

trdcycle	DMA Read Cycle Time	150 ns

Note Data is held until nDACK goes high regardless of state of nREAD.

Reset Timing

treset

nRST

tioact

nRD or nWR

Reset Timing

Parameter	Description	Min.	Typ.	Max.
tRESET	nRst Pulse width	16 clocks
tIOACT	nRst HIGH to nRD or nWR active	16 clocks

Note Clock is 48 MHz nominal.

Document 38-08008 Rev. *D

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Cypress SL811HS manual DMA Read Cycle, Reset Timing, NRst Pulse width, NRst High to nRD or nWR active

Contents

Introduction FeaturesMaster/Slave Controller Cypress Semiconductor Corporation Auto Address Increment Mode DMA Controller slave mode onlyData Port, Microprocessor Interface Interrupt Controller MHz Crystals SL811HS RegistersFrequency Tolerance USB Transceiver SL811HS Host Control Registers Register Values on Power Up and ResetUSB Control Registers HBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 ISOBit Position Bit Name Function HBL4 HBL3 HBL2 HBL1 HBL0 HBL7 HBL6PID Type D7-D4 HTC2 HTC7DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA7 USB Reset Sequence Low-power Modes Bit 6 Control Register, Address 05hControl Register 1 Address 05h Bit Control Register 1 Address 05h Bits 3 USB-B USB-A Interrupt Enable Register Address 06hDone USB-B Done Value of the Data+ pin Interrupt Status Register Address 0Dh BitUSB-B Revision Reserved Bit Position Bit Name Function SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoint Registers Register Name Miscellaneous register addressesEndpoints 0-3 Register Addresses Endpoints 0-3 Register Addresses Sequence Endpoint Control RegistersNext Data Set EPxLEN1 EPxLEN0 Transmission Acknowledge Reserved OverflowCurrent Data Set Register Control Register 0Fh SOF Low Byte Register Stbyd Control Register 1 Address 05hStbyd Spsel USB Address Register Address 07h USB Address Register, Address 07h. This registerUSBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 Interrupt Status Register Address 0Dh Control Register 2 Address 0Fh Bit Current Data Set Register Address 0EhReserved Master/Slave SL811HS Physical Connections Pin Plcc Mechanical DimensionsPin Plcc Physical Connections Pin Plcc Pin Layout Package Markings 28-pin Plcc Diagram below illustrates a simple +3.3V voltage source Pin Tqfp AXC Pin Layout Pin Tqfp Physical Connections Power for USB Transceivers . V DD1 may be connected to V DD 48/28-Pin USB Host Controller Pins Description Data 6. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 7. Microprocessor Data/Address Bus Buffer or register Package Markings 48-Pin Tqfp Yyww Xxxx Electrical Specifications DC Characteristics Parameter Description Min Typ Max Write Cycle Bus Interface Timing RequirementsParameter Description Min Typ Max NWR High Read Cycle DMA Write Cycle DMA Write Cycle DMA Read Cycle Reset TimingNRst Pulse width NRst High to nRD or nWR active Ordering Information Package DiagramsCLOCKClock TimingTIMING Parameter Description Min Typ Max Part Number Package Type Lead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 REV ECN no Issue Date Orig. Description of ChangeDocument History

Cypress SL811HS DMA Read Cycle, Reset Timing, NRst Pulse width, NRst High to nRD or nWR active

Models: SL811HS

DMA Read Cycle

SL811 DMA READ CYCLE TIMING

Parameter

Reset Timing

nRD or nWR

Reset Timing

Parameter

nRst Pulse width

nRst HIGH to nRD or nWR active