TMPR3901F

4.6 Reset

The TMPR3901F can be reset with the RESET* signal. The RESET* signal must be asserted for a certain number of R3900 Processor Core clock cycles in order for the TMPR3901F reset to take effect.

Since the RESET* signal is clock-synchronized with in the TMPR3901F, it can be asserted asynchronously .

TMPR3901F operations upon reset are as follows.

The pipeline stalls, and TMPR3901F internal states are initialized.

All valid bits and lock bits of the instruction and data caches are cleared.

During reset, the states of the output pins are as follows.

A [31:2]

undefined

D [31:0]

undefined

BE [3:0]*

H

RD*, WR*

H

BURST*

H

BSTSZ [1:0]

undefined

LAST*

H

BUSGNT*

H

HALT, DOZE

H

Data in the write buffer becomes invalid.

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Toshiba TX39 user manual Reset