Lock function, Lock bit setting | Toshiba TX39 specs

Architecture

Figure 7-4 shows the data cache address field.

31	9 8		1		0
Physical Tag			Cache Tag Index

Byte Select

Figure 7-4. Data cache address field

When a data store misses, the data is stored to main memory only, not to the cache (no write allocate).

The data cache can be written in individual bytes. (When a byte or halfword store is used, there is no read- modify-write.)

7.2.1Lock function

The lock function can be used to route critical data to one data cache set. Data is not replaced when the lock bit is set.

(1) Lock bit setting

Setting the Cache register DALc bit enables the data cache lock function. When data in a line is accessed, the lock bit for that line is set and data in the line can no longer be replaced. If a store miss occurs, the store data is not written to the cache and will therefore not be locked.

Note : When a block refill takes place, the size of data locked in the cache is the same as the block refill size.

The Cache register DALc bit can be set at the head of a subroutine or the like, thereby locking into the cache the data accessed by the subroutine. The lock function can be disabled by clearing the DALc bit. This does not clear the lock bits of individual lines.

(2) Operation during lock

When the lock bit is set for a line, only data in the set indicated by the LRU replace bit (R) can be replaced. A write access to a locked line takes place only to cache memory, without affecting main memory. When a lock has been established by the lock function, store operations can write to memory.

The Cache register lock bits form a three-layer stack consisting of DALc, DALp and DALo. If an exception is raised while the lock function is in effect, the stack is pushed (the DALc and DALp bit values are saved in DALp and DALo, respectively) and DALc is cleared, disabling the lock function. This is to prevent inadvertent locking of data used by the exception handler. After the handler has finished processing, a RFE instruction is executed, popping the stack (the DALo and DALp bit values are restored to DALp and DALc) and refurring the status to that prior to the exception.

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Toshiba TX39 user manual Lock function, Lock bit setting, Operation during lock

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 227 Bus request and bus grant 227 Cache snoop 228229 230 Architecture Architecture Introduction FeaturesHigh-performance Risc techniques Low power consumption Signal notation Notation Used in This ManualMathematical notation Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Instruction Set Overview Operation code 6 bitsSource register 5 bits Destination register 5 bits Load/store ComputationalJump/branch Coprocessor ALU Immediate Computational InstructionsALU 3-operand, register type Multiply/Divide Jump/Branch InstructionsCoprocessor Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview User mode Kernel modeMemory Management Unit MMU 1 R3900 Processor Core operating modes Direct segment mapping KusegKseg0 Kseg1 Address mapping Architecture Instruction Formats Instruction Set OverviewInstruction Notation Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Jump instructions Jump/Branch InstructionsInstruction Format and Description Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions COPz Instruction Format and Description Coprocessor InstructionsBCzT, BCzF Instruction Format and Description Architecture Restore From System Control Coprocessor CP0 Instructions13. System control coprocessor CP0 instructions Cache Instruction Format and Description Pipeline Architecture Delayed load Delay SlotDelayed branching Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Exception Processing Registers Cause registerStatus register Cache register Bits Mnemonic Field name Description Cause register register no.13Read/Write ExcCode field Mnemonic Cause Status register register no.12 BitsField name Description Read Status register 1/2 Bits Mnemonic Field name Description Value on Read KUc/KUp/KUo Kernel/User mode current/previous/old IEc/IEp/IEo Interrupt Enable current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details Address Error exception ∙ Causes ∙ Exception mask∙ Applicable instructions ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Return from Exception Handler Priority of ExceptionsPriority of Exceptions Exception Mnemonic Architecture Caches Instruction Cache Data cache configuration Data Cache Lock function Lock bit settingOperation during lock Lock bit clearing Auto-lock bits Cache Test Function Cache disablingCache flushing Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† DM Debug Mode 0 at reset DBD Debug Branch DelayDebug register register no.16 BsF Bus Error Exception Flag SSt Single at resetNIS Non-maskable Interrupt Status OES Other Exceptions Status Debug Exceptions DSS bitTypes of debug exceptions Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Executing a Deret instruction Iii Return from a debug exception handlerException priorities Single Step exception ∙ Cause Details of Debug Exceptions∙ Exception masking ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Word access 32 bits Triplebyte access 24 bitsHalfword access 16 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori Special function OPcodeCOPz rs COPz rt CP0 Function Notation TMPR3901F 200 On-chip peripheral circuits R3900 Processor CoreBus interface for ease of system implementation Low power consumption, optimal for portable applications Debugging support functions on chipMaximum operating frequency Package Internal Blocks R3900 Processor Core Clock generatorBus interface unit bus controller / write buffer Address protection unit 204 R3900 Processor Core ConfigurationInstruction Iimitations Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Debug Support Unit SynchronizerRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Enables internal PLL clock Mode quadruple frequency of crystal oscillatorHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze mode Operations Clock∙ Master Clock ∙ Processor Clock System clock Master clock ProcessorClock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode