Architecture

 

 

 

 

 

 

 

 

 

 

 

 

MTC0

 

 

Move To System Control Coprocessor

MTC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26 25

21 20

16 15

11 10

0

 

 

 

COP0

 

MT

 

rt

 

 

rd

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

010000

 

00100

 

 

 

 

 

 

000 0000 0000

 

 

6

5

5

 

 

5

 

11

 

 

Format :

MTC0 rt, rd

Description :

Loads the contents of general-purpose register rt into CP0 coprocessor register rd.

Executing this instruction may in some cases modify the state of the virtual address translation system, therefore the behavior of a load instruction, store instruction or TLB operation placed immediately before or after the MTC0 instruction cannot be defined.

Operation :

T:CPR[0, rd] GPR[rt]

Exceptions :

Coprocessor Unusable exception

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Image 173
Toshiba TX39 user manual MTC0