Architecture
162
MTC0 Move To System Control Coprocessor MTC0
31 26 25 21 20 16 15 1110 0
COP0
010000
MT
00100 rt rd 0
000 0000 0000
6 5 5 5 11
Format :
MTC0 rt, rd
Description :
Loads the contents of general-purpose register rt into CP0 coprocessor register rd.
Executing this instruction may in some cases modify the state of the virtual address translation
system, therefore the behavior of a load instruction, store instruction or TLB operation placed
immediately before or after the MTC0 instruction cannot be defined.
Operation :
T: CPR[0, rd] ← GPR[rt]
Exceptions :
Coprocessor Unusable exception