Architecture

 

 

 

 

 

 

 

 

 

 

 

 

MFC0

 

 

Move From System Control Coprocessor

MFC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31

26 25

21 20

16 15

11 10

0

 

 

 

COP0

 

MF

 

rt

 

 

rd

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

010000

 

00000

 

 

 

 

 

 

000 0000 0000

 

 

6

5

5

 

 

5

 

11

 

 

Format :

MFC0 rt, rd

Description :

Loads the contents of coprocessor CP0 register rd into general-purpose register rt.

Operation :

T:GPR[rt] CPR[0, rd]

Exceptions :

Coprocessor Unusable exception

157

Page 168
Image 168
Toshiba TX39 user manual MFC0