Bit# Cache Name, Data | Toshiba TX39 guide

Architecture

CACHE

Cache

CACHE

	31	26 25		21 20		16 15		0
		CACHE		base		op		offset
				base		op		offset
		101111
		6		5		5		16

Format :

CACHE op, offset(base)

Description :

Generates a virtual address by sign-extending the 16-bit offset and adding the result to the contents of register base. The virtual address is translated to a physical address, and a 5-bit sub-opcode designates the cache operation to be performed at that address.

If CP0 is unusable (in user mode), the Status register CP0 enable bit is cleared and a Coprocessor Unusable exception is raised. The behavior of this instruction for operation and cache combinations other than those listed in the table below, and when used with an uncached address, is undefined.

Cache index operations (shown for bits 20 through 18 below) designate a cache block using part of the virtual address.

For a directly mapped cache of 2CACHESIZE bytes with 2BLOCKSIZE bytes per tag, a block is designated as vAddrCACHESIZE-1 .. BLOCKSIZE. In the case of a 2WAYSIZE-way set-associative cache of 2CACHESIZE

BLOCKSIZE	WAYSIZE-1	.. BLOCKSIZE.
bytes with 2	bytes per tag, a set is designated as vAddrCACHESIZE-	.. BLOCKSIZE.

A Cache hit operation (shown for bits 20 through 18 below) accesses the designated cache as an ordinary data reference. If a cache block contains valid data for the generated physical address, it is a hit and the designated operation is performed. In case of a miss, that is, if the cache block is invalid or contains a different address, no operation is performed.

Bits 17..16 of the Cache instruction select the target cache as follows.

	Bit#		Cache	Cache
17		16	ID	Name

0		0	I	Instruction
0		1	D	Data
1		0	-	(reserved)
1		1	-	(reserved)

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Image 144

Toshiba TX39 user manual Bit# Cache Name, Data

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 227 Bus request and bus grant 227 Cache snoop 228229 230 Architecture Architecture Features IntroductionHigh-performance Risc techniques Low power consumption Signal notation Notation Used in This ManualMathematical notation Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Instruction Set Overview Operation code 6 bitsSource register 5 bits Destination register 5 bits Load/store ComputationalJump/branch Coprocessor Computational Instructions ALU ImmediateALU 3-operand, register type Multiply/Divide Jump/Branch InstructionsCoprocessor Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview User mode Kernel modeMemory Management Unit MMU 1 R3900 Processor Core operating modes Direct segment mapping KusegKseg0 Kseg1 Address mapping Architecture Instruction Set Overview Instruction FormatsInstruction Notation Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Jump/Branch Instructions Jump instructionsInstruction Format and Description Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions Coprocessor Instructions COPz Instruction Format and DescriptionBCzT, BCzF Instruction Format and Description Architecture Restore From System Control Coprocessor CP0 Instructions13. System control coprocessor CP0 instructions Cache Instruction Format and Description Pipeline Architecture Delay Slot Delayed loadDelayed branching Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Exception Processing Registers Cause registerStatus register Cache register Cause register register no.13 Bits Mnemonic Field name DescriptionRead/Write ExcCode field Mnemonic Cause Status register register no.12 BitsField name Description Read Status register 1/2 Bits Mnemonic Field name Description Value on Read KUc/KUp/KUo Kernel/User mode current/previous/old IEc/IEp/IEo Interrupt Enable current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details Address Error exception ∙ Causes ∙ Exception mask∙ Applicable instructions ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Priority of Exceptions Return from Exception HandlerPriority of Exceptions Exception Mnemonic Architecture Caches Instruction Cache Data cache configuration Data Cache Lock bit setting Lock functionOperation during lock Lock bit clearing Auto-lock bits Cache Test Function Cache disablingCache flushing Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† DBD Debug Branch Delay DM Debug Mode 0 at resetDebug register register no.16 BsF Bus Error Exception Flag SSt Single at resetNIS Non-maskable Interrupt Status OES Other Exceptions Status Debug Exceptions DSS bitTypes of debug exceptions Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Iii Return from a debug exception handler Executing a Deret instructionException priorities Details of Debug Exceptions Single Step exception ∙ Cause∙ Exception masking ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Word access 32 bits Triplebyte access 24 bitsHalfword access 16 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori OPcode Special functionCOPz rs COPz rt CP0 Function Notation TMPR3901F 200 R3900 Processor Core On-chip peripheral circuitsBus interface for ease of system implementation Low power consumption, optimal for portable applications Debugging support functions on chipMaximum operating frequency Package Internal Blocks R3900 Processor Core Clock generatorBus interface unit bus controller / write buffer Address protection unit 204 Configuration R3900 Processor CoreInstruction Iimitations Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Debug Support Unit SynchronizerRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Enables internal PLL clock Mode quadruple frequency of crystal oscillatorHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze mode Operations Clock∙ Master Clock ∙ Processor Clock Master clock Processor System clockClock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode