Architecture
116
BEQ Branch On Equal BEQ
31 26 25 21 20 1615 0
BEQ
000100 rs rt offset
6 5 5 16
Format :
BEQ rs, rt, offset
Description :
Generates a branch target address by adding the address of the instruction in the delay slot to the 16-
bit offset (that has been left-shifted two bits and sign-extended to 32 bits). The contents of general
registers rs and rt are compared and, if equal, the program branches to the target address after a one-
cycle delay.
Operation :
T:
T + 1:
target ← (offset15)14 || offset || 02
condition ← (GPR[rs] = GPR[rt])
if condition then
PC ← PC + target
endif
Exceptions :
None