Architecture
148
LHU Load Halfword Unsigned LHU
31 26 25 21 20 16 15 0
LHU
100101 base rt offset
6 5 5 16
Format :
LHU rt, offset(base)
Description :
Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents
of general-purpose register base. It then zero-extends the halfword at the memory location pointed
to by the effective address and loads the result into general-purpose register rt.
If the effective address is not aligned on a halfword boundary, i.e., if the least significant bit of the
effective address is not 0, an Address Error exception is raised.
Operation :
T: vAddr ← ((offset15)16 || offset15..0) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr31..2 || (pAddr1..0 xor (ReverseEndian || 0))
mem ← LoadMemory (uncached, HALFWORD, pAddr, vAddr, DATA)
byte ← vAddr1..0 xor BigEndianCPU || 0)
GPR[rt] ← 0 16 || mem15+8*byte..8*byte
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
Address Error exception