Toshiba TX39 user manual Pipeline Processing Overview

Architecture

2.5 Pipeline Processing Overview

The R3900 Processor Core executes instructions in five pipeline stages (F: instruction fetch; D: decode; E:

execute; M: memory access; W: register write-back). Each pipeline stage is executed in one clock cycle. When the pipeline is fully utilized, five instructions are executed at the same time resulting in an instruction execution rate of one instruction per cycle.

With the R3900 Processor Core an instruction that immediately follows a load instruction can use the result of that load instruction. Execution of the following instruction is delayed by hardware interlock until the result of the load instruction becomes available. The instruction position immediately following the load instruction is called the “load delay slot.”

In the case of branch instructions, a one-cycle delay is required to generate the branch target address. This delayed cycle is referred to as the “branch delay slot.” An instruction placed immediately after a branch instruction (in the branch delay slot) can be executed prior to the branch while the branch target address is being generated.

The R3900 Processor Core provides a Branch Likely instruction whereby an instruction to be executed at the branch target can be placed in the delay slot of the Branch Likely instruction and executed only if the conditions of the branch instruction are met. If the conditions are not met, and the branch is not taken, the instruction in the delay slot is treated as a NOP. This makes it possible to place an instruction that would normally be executed at the branch target into the delay slot for quick execution (if the conditions of the branch are met).

F	D	E	M	W
	F	D	E	M	W
		F	D	E	M	W
			F	D	E	M	W
				F	D	E	M	W

Current CPU

cycle

Figure 2-7. Pipeline stages for execution of R3900 Processor Core instructions

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