Toshiba TX39 user manual Data Cache, Data cache configuration

Architecture

7.2 Data Cache

The data cache has the following specifications.

− Cache size : 1 Kbyte (Config register DCS bits = 000)

−Two-way set-associative

−Replace algorithm : LRU (Least Recently Used)

− Block (line) size : 1 word (4 bytes)

−Write-through

−Physical cache

− Refill size : Choice of size 1/4/8/16/32 words (set in Config register)

−Byte-writable

−All valid bits and lock bits cleared by a Reset exception

−Lock function

Figure 7-3 shows the data cache configuration.

set : 0 1

Set address :

127	R	L
3	R	L
2	R	L
1	R	L
0	R	L

23	22	0
V		Physical Tag

VPhysical Tag

V Physical Tag

V Physical Tag

V Physical Tag

310

Data

Data

Data

Data

Data

23	22	0
V		Physical Tag

VPhysical Tag

V Physical Tag

V Physical Tag

V Physical Tag

310

Data

Data

Data

Data

Data

R : LRU replace bit(indicates next set to which replacement will be directed; when lock bit is set to 1,indicates this set is not locked)

L : Lock bit(when set to 1,if R bit is 1,set 0 is locked, and if R bits 0,set 1 is locked; when cleared to 0,lock function is disabled)

V : valid bit(1=valid;0=invalid)

Figure 7-3. Data cache configuration

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