Architecture

3.7 Coprocessor Instructions

Coprocessor instructions invoke coprocessor operations. The format of these instructions depends on which

coprocessor is used.

Table 3-12. Coprocessor instructions

(a) MTCz, MFCz, CTCz, CFCz

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

op

funct

 

rt

rd

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Move To

MTCz rt, rd

 

 

 

 

 

 

 

 

 

Coprocessor

Move the contents of CPU general register rt to coprocessor z’s coprocessor

 

register rd.

 

 

 

 

 

 

 

 

 

Move From

MFCz rt, rd

 

 

 

 

 

 

 

 

 

Coprocessor

Move the contents of coprocessor z’s coprocessor register rd to CPU general

 

register rt.

 

 

 

 

 

 

 

 

 

Move Control

CTCz rt, rd

 

 

 

 

 

 

 

 

 

To

Move the contents of CPU general register rt to coprocessor z’s coprocessor

Coprocessor

control register rd.

 

 

 

 

 

 

 

 

 

Move Control

CFCz rt, rd

 

 

 

 

 

 

 

 

 

From

Move the contents of coprocessor z’s coprocessor control register rd to CPU

Coprocessor

general register rt.

 

 

 

 

 

 

 

 

 

 

(b)

COPz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

 

op

 

co

 

 

 

cofun

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Coprocessor

COPz cofun

 

 

 

 

 

 

 

 

 

Operation

Execute in coprocessor z the processing indicated in cofun.

The CPU state is

 

not changed by the processing executed in the coprocessor.

 

 

 

(c) BCzT, BCzF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

op

 

funct

 

 

offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Branch on

BCzT offset

 

 

 

 

 

 

 

 

 

Coprocessor

Generate the branch target address by adding the address of the instruction in

z True

the delay slot (the instruction to be executed during the branch) and the 16-bit

 

offset (after left-shifting two bits and sign-extending to 32 bits). If the

 

coprocessor z condition line is true, branch to the target address after a one-

 

cycle delay.

 

 

 

 

 

 

 

 

 

Branch on

BCzF offset

 

 

 

 

 

 

 

 

 

Coprocessor

Generate the branch target address by adding the address of the instruction in

z False

the delay slot (the instruction to be executed during the branch) and the 16-bit

 

offset (after left-shifting two bits and sign-extending to 32 bits). If the

 

coprocessor z condition line is false, branch to the target address after a one-

 

cycle delay.

 

 

 

 

 

 

 

 

 

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Toshiba TX39 user manual Coprocessor Instructions, COPz Instruction Format and Description